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Hardware Implementations of Pairings at Updated Security Levels

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Smart Card Research and Advanced Applications (CARDIS 2021)

Abstract

Pairings are cornerstones to several interesting cryptographic protocols including Non-interactive ARgument of Knowledge currently used in Zcash cryptocurrency. The Kim and Barbulescu Number Field Sieve attack has weakened pairing-friendly curves. Most impacted are the famous BN curves which now require an increase of the parameters to provide equivalent security. Recent cost estimations of pairings have recommended switching to other curves, but their selections are no longer clearly straightforward. This paper aims at providing the first hardware-based pairing implementations on the best curve candidates at both 128-bit and 192-bit security levels. The proposed architecture intends to fit both lightweight FPGA and ASIC purposes and the design is prototyped on a Kintex-7 FPGA device. It computes a pairing within 42.7 ms for 128-bit of security and 184.2 ms for 192-bit.

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Notes

  1. 1.

    At the time of submitting this article, the proposed formula was new in the literature. However, we later realized that it also appears in the RELIC project [1].

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Correspondence to Arthur Lavice .

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Lavice, A., Mrabet, N.E., Berzati, A., Rigaud, JB., Proy, J. (2022). Hardware Implementations of Pairings at Updated Security Levels. In: Grosso, V., Pöppelmann, T. (eds) Smart Card Research and Advanced Applications. CARDIS 2021. Lecture Notes in Computer Science(), vol 13173. Springer, Cham. https://doi.org/10.1007/978-3-030-97348-3_11

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  • DOI: https://doi.org/10.1007/978-3-030-97348-3_11

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