Abstract
The appendix of the book first reviews the promise and challenges for machine learning (ML) in physical design and illustrates benefits that can be achieved in terms of schedule and quality of results, as demonstrated in recent publications (Sect. 9.1). This first part of the appendix identifies a number of useful surveys and reviews ML-based methods that can be applied to tasks addressed in the preceding chapters of the book. Section 9.2 presents detailed solutions to the exercises of Chaps. 2–8. Finally, Sect. 9.3 depicts layout examples of typical CMOS-library cells, such as the inverter, buffer, NAND and NOR gates, and an AND-OR-Invert gate.
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Kahng, A.B., Lienig, J., Markov, I.L., Hu, J. (2022). Appendix. In: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, Cham. https://doi.org/10.1007/978-3-030-96415-3_9
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