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Detailed Routing

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VLSI Physical Design: From Graph Partitioning to Timing Closure

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Abstract

Following global routing, each net undergoes detailed routing. The objective of detailed routing is to assign route segments of signal nets to specific routing tracks, vias, and metal layers in a manner consistent with given global routes of those nets. Traditional detailed routing techniques are applied within routing regions, such as channels (Sect. 6.3) and switch boxes (Sect. 6.4). For modern designs, over-the-cell (OTC) or gcell routing (Sect. 6.5) allows wires to be routed over (standard) cells based on their gcell assignments. Due to technology scaling, modern detailed routers must account for additional manufacturing rules and the impact of manufacturing faults and resolution (Sect. 6.6).

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References

  1. C. J. Alpert, Z. Li, M. D. Moffitt, G.-J. Nam, J. A. Roy and G. Tellez, “What Makes a Design Difficult to Route”, Proc. Int. Symp. on Physical Design, 2010, pp. 7-12. https://doi.org/10.1145/1735023.1735028

  2. D. Braun et al., “Techniques for Multilayer Channel Routing”, IEEE Trans. on CAD 7(6) (1988), pp. 698-712. https://doi.org/10.1109/43.3209

    Article  Google Scholar 

  3. J. P. Cohoon and P. L. Heck, “BEAVER: A Computational-Geometry-Based Tool for Switchbox Routing”, IEEE Trans. on CAD 7(6) (1988), pp. 684-697. https://doi.org/10.1109/43.3208

    Article  Google Scholar 

  4. J. Cong and C. L. Liu, “Over-the-Cell Channel Routing”, IEEE Trans. on CAD 9(4) (1990), pp. 408-418. https://doi.org/10.1109/ICCAD.1988.122467

    Article  Google Scholar 

  5. J. Cong, D. F. Wong and C. L. Liu, “A New Approach to Three- or Four-Layer Channel Routing”, IEEE Trans. on CAD 7(10) (1988), pp. 1094-1104. https://doi.org/10.1109/43.7808

    Article  Google Scholar 

  6. D. N. Deutsch, “A ‘Dogleg’ Channel Router”, Proc. Design Autom. Conf., 1976, pp. 425-433. https://doi.org/10.1145/800146.804843

  7. S. H. Gerez and O. E. Herrmann, “Switchbox Routing by Stepwise Reshaping”, IEEE Trans. on CAD 8(12) (1989), pp. 1350-1361. https://doi.org/10.1109/43.44515

    Article  Google Scholar 

  8. A. Hashimoto and J. Stevens, “Wire Routing by Optimizing Channel Assignment within Large Apertures”, Proc. Design Autom. Workshop, 1971, pp. 155-169. https://doi.org/10.1145/800158.805069

  9. T.-T. Ho, S. S. Iyengar and S.-Q. Zheng, “A General Greedy Channel Routing Algorithm”, IEEE Trans. on CAD 10(2) (1991), pp. 204-211. https://doi.org/10.1109/43.68407

    Article  Google Scholar 

  10. N. D. Holmes, N. A. Sherwani and M. Sarrafzadeh, “Utilization of Vacant Terminals for Improved Over-the-Cell Channel Routing”, IEEE Trans. on CAD 12(6) (1993), pp. 780-792. https://doi.org/10.1109/43.229752

    Article  Google Scholar 

  11. M. Ahrens et al., “Detailed Routing Algorithms for Advanced Technology Nodes”, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 34, no. 4, pp. 563-576, Apr. 2015. https://doi.org/10.1109/TCAD.2014.2385755

    Article  Google Scholar 

  12. M. Gester et al., “BonnRoute: Algorithms and Data Structures for Fast and Good VLSI Routing”, ACM Trans. Design Automat. Electron. Syst., vol. 18, no. 2, pp. 1-24, 2013. https://doi.org/10.1145/2442087.2442103

    Article  Google Scholar 

  13. Y. Zhang and C. Chu, “RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 9, pp. 1655-1668, Sep. 2013. https://doi.org/10.1109/TVLSI.2012.2214491

    Article  Google Scholar 

  14. S. M. M. Gonçalves, L. S. da Rosa and F. S. de Marques, “An Improved Heuristic Function for A*-based Path Search in Detailed Routing”, Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1-5, 2019. https://doi.org/10.1109/ISCAS.2019.8702460

    Article  Google Scholar 

  15. S. M. M. Gonçalves, L. S. da Rosa and F. de S. Marques, “DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing”, IEEE Trans. Circuits Syst. II Exp. Briefs, 2019. https://doi.org/10.1109/TCSII.2019.2937893

  16. A. B. Kahng, L. Wang and B. Xu, “TritonRoute: The Open-Source Detailed Router,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 40, no. 3, pp. 547-559, 2021. https://doi.org/10.1109/TCAD.2020.3003234.

    Article  Google Scholar 

  17. W. K. Luk, “A Greedy Switchbox Router”, Integration, the VLSI J. 3(2) (1985), pp. 129-149. https://doi.org/10.1016/0167-9260(85)90029-X

    Article  Google Scholar 

  18. J. K. Ousterhout et al., “Magic: A VLSI Layout System”, Proc. Design Autom. Conf., 1984, pp. 152-159. https://doi.org/10.1109/DAC.1984.1585789

  19. R. Rivest and C. Fiduccia, “A ‘Greedy’ Channel Router”, Proc. Design Autom. Conf., 1982, pp. 418-424. https://doi.org/10.1109/DAC.1982.1585533

  20. G. Xu, L.-D. Huang, D. Pan and M. Wong, “Redundant-Via Enhanced Maze Routing for Yield Improvement”, Proc. Asia and South Pacific Design Autom. Conf., 2005, pp. 1148-1151. https://doi.org/10.1109/ASPDAC.2005.1466544

  21. T. Yoshimura, “An Efficient Channel Router”, Proc. Design Autom. Conf., 1984, pp. 38-44. https://doi.org/10.1109/DAC.1984.1585770

  22. T. Yoshimura and E. S. Kuh, “Efficient Algorithms for Channel Routing”, IEEE Trans. on CAD 1(1) (1982), pp. 25-35. https://doi.org/10.1109/TCAD.1982.1269993

    Article  Google Scholar 

  23. Int. Roadmap for Devices and Systems (IRDS), 2021 Edition. https://irds.ieee.org/editions. Accessed 1 Jan. 2022.

  24. J. Lienig, J. Scheible, Fundamentals of Layout Design for Electronic Circuits. Springer, 2020. ISBN 978-3-030-39283-3, 2020. https://doi.org/10.1007/978-3-030-39284-0

  25. J. Lienig, M. Thiele, Fundamentals of Electromigration-Aware Integrated Circuit Design, Springer, 2018. ISBN 978-3-319-73557-3. https://doi.org/10.1007/978-3-319-73558-0

  26. J. Lienig, M. Thiele, “The Pressing Need for Electromigration-Aware Integrated Circuit Design”, Proc. Int. Symp. on Phys. Design, 2018, pp. 144-151. https://doi.org/10.1145/3177540.3177560

  27. A. Kahng, B. Liu and I. Mǎndoiu, “Non-Tree Routing for Reliability and Yield Improvement”, Proc. Int. Conf. on CAD, 2002, pp. 260-266. https://doi.org/10.1109/ICCAD.2002.1167544

  28. N. Dhumane, S. K. Srivathsa and S. Kundu, “Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability,” 2011 IEEE Computer Society Annual Symposium on VLSI, 2011, pp. 200-205. https://doi.org/10.1109/ISVLSI.2011.32

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. Departments of CSE and ECE, University of California at San Diego, La Jolla, CA, USA

    Andrew B. Kahng

  2. Electrical and Computer Engineering, TU Dresden, Dresden, Saxony, Germany

    Jens Lienig

  3. University of Michigan, Currently at: Meta Platforms, Inc, Ann Arbor, MI, USA

    Igor L. Markov

  4. University of Michigan, Currently at: Two Sigma Insurance Quantified, LP, New York, NY, USA

    Jin Hu

Authors
  1. Andrew B. Kahng
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  2. Jens Lienig
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  3. Igor L. Markov
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  4. Jin Hu
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Exercises

Exercises

Exercise 1: Left-Edge Algorithm

Given a channel with the following pin connections (ordered left to right):

TOP = [A B A 0 E D 0 F] and BOT = [B C D A C F E 0]

  1. (a)

    Find S(col) for columns a–h and the minimum number of routing tracks.

  2. (b)

    Draw the HCG and VCG.

  3. (c)

    Use the left-edge algorithm to route this channel. For each track, mark the placed nets and draw the updated VCG from (b). Draw the channel with the fully routed nets.

Exercise 2: Dogleg Left-Edge Algorithm

Given a channel with the following pin connections (ordered left to right):

TOP = [A A B 0 A D C E] and BOT = [0 B C A C E D D]

  1. (a)

    Draw the vertical constraint graph (VCG) without splitting the nets.

  2. (b)

    With net splitting, determine the zone representation for nets A–E. Find S(col) for columns a–h.

  3. (c)

    Draw the vertical constraint graph (VCG) with net splitting.

  4. (d)

    Find the minimum number of required tracks with net splitting and without net splitting.

  5. (e)

    Use the Dogleg left-edge algorithm to route this channel. For each track, state which nets are assigned. Draw the final routed channel.

Exercise 3: Switchbox Routing

Given the nets on each side of a switchbox (ordered bottom-to-top) LEFT = [0 G A F B 0] RIGHT = [0 D C E G 0] and (ordered left-to-right) BOT = [0 A F G D 0] TOP  = [0 A C E B D]:

Route the switchbox using the approach shown in the example in Sect. 6.4.2. For each column, mark the routed nets and their corresponding tracks. Draw the switch box with all nets routed.

Exercise 4: Manufacturing Defects

Consider a region with high wiring congestion and a region where routes can be completed easily. For each type of manufacturing defect discussed in Sect. 6.6, is it more likely to occur in a congested region? Explain your answers. You may find it useful to visualize congested and uncongested regions using small examples.

Exercise 5: Modern Challenges in Detailed Routing

Develop an algorithmic approach to double-via insertion.

Exercise 6: Non-tree Routing

Discuss advantages and drawbacks of non-tree routing (Sect. 6.6).

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Kahng, A.B., Lienig, J., Markov, I.L., Hu, J. (2022). Detailed Routing. In: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, Cham. https://doi.org/10.1007/978-3-030-96415-3_6

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  • DOI: https://doi.org/10.1007/978-3-030-96415-3_6

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  • Online ISBN: 978-3-030-96415-3

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