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Global and Detailed Placement

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VLSI Physical Design: From Graph Partitioning to Timing Closure

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Abstract

After partitioning the circuit into smaller modules (Chap. 2) and floorplanning the layout to determine the outlines and positions of blocks and their pin locations (Chap. 3), placement seeks to determine the locations of (standard) cells or logic elements within each block. Placement is subject to multiple optimization objectives, a common one being the minimization of the total length of connections between elements. Global placement (Sect. 4.3) assigns general locations to movable objects, which is then followed by detailed placement (Sect. 4.4), which refines object locations to legal cell sites and enforces nonoverlapping constraints.

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Notes

  1. 1.

    Timing-driven placement techniques are discussed in Chap. 8 (Sect. 8.3).

  2. 2.

    Such an edge represents the border between two regions (e.g., switchboxes or channels) or between two cutlines.

  3. 3.

    simPL uses FastPlace-DP [22] for both legalization and detailed placement.

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Author information

Authors and Affiliations

  1. Departments of CSE and ECE, University of California at San Diego, La Jolla, CA, USA

    Andrew B. Kahng

  2. Electrical and Computer Engineering, TU Dresden, Dresden, Saxony, Germany

    Jens Lienig

  3. University of Michigan, Currently at: Meta Platforms, Inc, Ann Arbor, MI, USA

    Igor L. Markov

  4. University of Michigan, Currently at: Two Sigma Insurance Quantified, LP, New York, NY, USA

    Jin Hu

Authors
  1. Andrew B. Kahng
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  2. Jens Lienig
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  3. Igor L. Markov
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Exercises

Exercises

Exercise 1: Estimating Total Wirelength

Consider the five-pin net with pins a–e (right). Each grid edge has unit length.

(a) Draw a rectilinear minimum-length chain, a rectilinear minimum spanning tree (RMST), and a rectilinear Steiner minimum tree (RSMT) to connect all pins.

(b) Find the weighted total wirelength using each estimation technique from (a) if each grid edge has weight = 2.

Exercise 2: Min-Cut Placement

Perform min-cut placement to place gates a–g on a 2 × 4 grid. Use the Kernighan–Lin algorithm for partitioning. Use alternating (horizontal and vertical) cutlines. The cutline cut1 represents the initial vertical cut. Each edge on the grid has capacity σP(e) = 2. Estimate whether the placement is routable.

Exercise 3: Force-Directed Placement

A circuit with two gates a and b and three I/O pads In1 (0,2), In2 (0,0), and Out (2,1) is given (left). The weights of the connections are shown below. Calculate the ZFT positions of the two gates. Place the circuit on a 3 × 3 grid (right).

figure aq

Exercise 4: Global and Detailed Placement

What are the main differences between global and detailed placement? Explain why the global and detailed placement steps are performed separately. Explain why detailed placement follows global placement.

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Kahng, A.B., Lienig, J., Markov, I.L., Hu, J. (2022). Global and Detailed Placement. In: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, Cham. https://doi.org/10.1007/978-3-030-96415-3_4

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  • DOI: https://doi.org/10.1007/978-3-030-96415-3_4

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