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Chip Planning

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VLSI Physical Design: From Graph Partitioning to Timing Closure

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Abstract

Chapter 3 is dedicated to chip planning, which includes floorplanning, pin assignment (I/O assignment), and power-ground planning. Floorplanning (Sects. 3.1–3.5) determines the locations and dimensions of the shapes that are the result of partitioning the entire circuit (Chap. 2). Hence, floorplanning produces assigned blocks and enables early estimates of interconnect length, circuit delay, and chip performance. Pin assignment (Sect. 3.6) assigns outgoing signal nets to block pins. Pin assignment directly influences the quality of the floorplan, especially the wiring length. Therefore, floorplanning and pin assignment are generally closely coupled or even combined as a single step. Finally, power planning (Sect. 3.7) builds the power supply network, i.e., power and ground nets, so as to ensure that each block is provided with appropriate supply voltage.

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Notes

  1. 1.

    A supply I/O pad can deliver tens of milliamperes of current, while a supply bump can deliver hundreds of milliamperes, i.e., an order of magnitude more current.

  2. 2.

    Some design manuals will refer to an IR drop limit of 10% of VDD. This means that the supply can drop (droop) by 5% of VDD and the ground can bounce by 5% as well, resulting in a worst case of 10% supply reduction.

References

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Author information

Authors and Affiliations

  1. Departments of CSE and ECE, University of California at San Diego, La Jolla, CA, USA

    Andrew B. Kahng

  2. Electrical and Computer Engineering, TU Dresden, Dresden, Saxony, Germany

    Jens Lienig

  3. University of Michigan, Currently at: Meta Platforms, Inc, Ann Arbor, MI, USA

    Igor L. Markov

  4. University of Michigan, Currently at: Two Sigma Insurance Quantified, LP, New York, NY, USA

    Jin Hu

Authors
  1. Andrew B. Kahng
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  2. Jens Lienig
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  3. Igor L. Markov
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  4. Jin Hu
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Exercises

Exercises

Exercise 1: Slicing Trees and Constraint Graphs

For the given floorplan (right), generate its slicing tree, vertical constraint graph, and horizontal constraint graph.

Exercise 2: Floorplan Sizing Algorithm

Three blocks a, b, and c are given along with their size options.

figure ad
  1. (a)

    Determine the shape functions for each block A, B, and C.

  2. (b)

    Find the minimum area of the top-level floorplan using the given tree structure and determine the shape function of the top-level floorplan. In the shape function, find the corner point that yields the minimal area. Finally, determine the dimensions of each block and draw the resulting floorplan.

figure ae

Exercise 3: Linear Ordering Algorithm

For the given netlist with five blocks a–e and six nets N1–N6, determine the linear ordering that minimizes the total wirelength. Let the starting block be block a. Place it in the first (leftmost) position. Draw the resulting placement.

Exercise 4: Non-slicing Floorplans

Recall that the smallest non-slicing floorplans with no wasted space exhibit the structure of a clockwise or counterclockwise wheel with five blocks. Draw a non-slicing floorplan with only four blocks a–d.

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Kahng, A.B., Lienig, J., Markov, I.L., Hu, J. (2022). Chip Planning. In: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, Cham. https://doi.org/10.1007/978-3-030-96415-3_3

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  • DOI: https://doi.org/10.1007/978-3-030-96415-3_3

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  • Online ISBN: 978-3-030-96415-3

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