Abstract
Quantization is the second main process in conversion. This chapter deals with the mathematical derivation and modeling of quantization in several resolution ranges. Quantization results in several specific parameters: integral and differential linearities and derived problems such as monotonicity. Various shapes of non-linearity are discussed and the relation to harmonic distortion is explained. The signal-to-noise ratio is also affected by quantization. The effect of dither and the relation between differential non-linearity and signal-to-noise are examined.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Truncation means that the additional fraction of the signal above the reference level is ignored.
- 2.
Other coding schemes will appear when discussing the implementation of complex converters, for instance, locally ternary (three-level) coding can be used in full-differential implementations. In error correction schemes, a base lower than 2 is applied.
- 3.
A group of 8 bits is referred to as 1 byte, irrespective of whether it represents a sample or other data. A speed of 1 GB/s is therefore equivalent to 8 Gb/s. Watch out for upper or lower case “b,B.”
- 4.
- 5.
Other binary code formats are discussed in paragraph 11.1.1.
- 6.
Naming the coefficients is a somewhat double-edged choice. When the LSB uses the index “0,” the mathematical link to the exponent is easy: b020. The consequence is that the MSB carries the index N − 1 as in bN−1, which is counter intuitive for a resolution N. Naming the MSB, bN requires to subtract in the exponent: bN2N−1, which is really confusing.
- 7.
N. Blachman has mathematically analyzed many processes around quantization. His publications from 1960 to 1985 form a good starting point to dive deeper in this field, for instance, [6].
- 8.
And for some smart students of course, who will notice that this DC-shift changes the truncation operation into rounding.
- 9.
Note that in a formal sense just voltage-squared is calculated, which lacks the impedance level and the time span needed to reach the dimension of power: Watt or V2/Ωsec. In quantization theory, “voltage-squared” power is only used to compare to another “voltage-squared” power, assuming that both relate to the same impedance level and the same time span. This quantization error becomes visible to an engineer (mostly) as part of a power spectrum. For that reason this book prefers the term quantization power instead of energy.
- 10.
The second law states that the entropy of a closed system cannot decrease, or the non-entropy energy will evolve to a minimum.
- 11.
As the habit is to call quantization errors “noise,” the “N” in SNQR is kept, the subscript “Q” indicates that quantization is meant.
- 12.
A THD of −43.8 dB is shorthand for 10−43.8∕10 = 4.167 × 10−5 power ratio. Use the exponential notation in complex calculations, as most modern engineers are not educated with logarithms.
- 13.
A manipulation like this is aversely coined: “specmanship”.
- 14.
Non-English speakers often confuse monotonic with monotonous which is synonymous to boring, dull, uninteresting.
- 15.
This is a bit of hand-waving statistics. A real formal derivation takes a page.
- 16.
There has been an extensive search for optimum dither signals in the 1960s–1970s. Wadgy and Goff [16] provides a theoretical background. Today, dither is actively used to mitigate conversion artifacts. The concept provides also valuable insight, for instance, sigma-delta modulators (Σ Δ) can be understood as low-resolution converters that generate their own dither.
- 17.
Although useful as a measure of performance, the importance of an F.o.M. should not be overemphasized. On the ISSCC in the same year, a span of over 100 × can be seen, which displays that other performance aspects dominate.
- 18.
The author of this book was educated with the notion that “log” operations can only be performed on dimensionless quantities. Obviously, this is not the case here.
- 19.
In the evolution of the F.o.M., the equation was inverted, leading to the counterintuitive behavior that a low F.o.M. number is better than a high one.
- 20.
The Signal-to-Noise Ratio is the ratio between signal power and noise power, for instance, 2000. In many notations not this number but its \(10\log ()\) is used, here: 33 dB. Whenever the SNR is used in calculations, the ratio number is used, not the dB value.
- 21.
Compared to Moore’s law for digital circuits from the previous decades, where speed doubles and area and power halve for every generation (2 years), this is a meager result.
- 22.
A memory designer once said “it is not a matter whether a memory device meets the specifications, the discriminating factor is how far a device can be used outside its specifications.”
References
A. Harley Reeves, Electric signaling system, U.S. Patent 2-272-070, issued February 3, 1942. Also French Patent 852-183 issued 1938, and British Patent 538–860 issued 1939
IEEE Std 1057-1994, IEEE Standard for Digitizing Waveform Recorders (1994)
IEEE 1241-2000, Standard For Terminology and Test Methods for Analog-to-digital Converters, IEEE Std1241, 2000. ISBN:0-7381-2724-8, revision 2007
S.J. Tilden, T.E. Linnenbrink, P.J. Green, Overview of IEEE-STD-1241 standard for terminology and test methods for analog-to-digital converters, in Instrumentation and Measurement Technology Conference, pp. 1498–1503 (1999)
W.R. Bennett, Spectra of quantized signals. Bell Syst. Tech. J. 27, 446–472 (1948)
N. Blachman, The intermodulation and distortion due to quantization of sinusoids. IEEE Trans. Acoust. Speech Signal Process. ASSP 33, 1417–1426 (1985)
M.S. Oude Alink, A.B.J. Kokkeler, E.A.M. Klumperink, K.C. Rovers, G. Smit, B. Nauta, Spurious-free dynamic range of a uniform quantizer. IEEE Trans. Circuits Syst. II Express Briefs 56, 434–438 (2009)
S. Lloyd, Least squares quantization in PCM. IEEE Trans. Inf. Theory 28, 129–137 (1982); (transcript from 1957 paper)
J. Max, Quantizing for minimum distortion. IRE Trans. Inf. Theory 6, 7–12 (1960)
A. Shikata, R. Sekimoto, T. Kuroda, H. Ishikuro, A 0.5 V 1.1 MS/s 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS. IEEE J. Solid State Circuits 47, 1022–1030 (2012)
W. Sansen, Distortion in elementary transistor circuits. IEEE Trans. Circuits Syst. II 46, 315–325 (1999)
A. Ramkaj et al., A 5-GS/s 158.6-mW 9.4-ENOB passive-sampling time-interleaved three-stage pipelined-SAR ADC with analog-digital corrections in 28-nm CMOS. IEEE J. Solid State Circuits 55, 1553–1564 (2020)
M.J.M. Pelgrom, A.C.v. Rens, M. Vertregt, M.B. Dijkstra, A 25-MS/s 8-bit CMOS A/D converter for embedded application. IEEE J. Solid State Circuits 29, 879–886 (1994)
S.P. Lipshitz, R.A. Wannamaker, J. Vanderkooy, Quantization and dither: A theoretical study. J. Audio Eng. Soc. 40, (1992)
R.A. Wannamaker, S.P. Lipshitz, J. Vanderkooy, J.N. Wright, A theory of nonsubtractive dither. IEEE Trans. Signal Process. 48, 499–516 (2000)
M. Wagdy, M. Goff, Linearizing average transfer characteristics of ideal ADC’s via analog and digital dither. IEEE Trans. Instrum. Meas. 43, 146–150 (1994)
J.L. Ceballos, I. Galton, G.C. Temes, Stochastic analog-to-digital conversion, in IEEE Midwest Symposium Circuits Systems, pp. 855–858 (2005)
R. Kapusta et al., A 14-b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS. IEEE J. Solid State Circuits 48, 3059–3066 (2013)
Devarajan et al., A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology. IEEE J. Solid State Circuits 52, 3204–3215 (2017)
A.M.A. Ali et al., A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration. IEEE J. Solid State Circuits 49, 2857–2867 (2014)
M. Straayer et al., A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth, in International Solid-State Circuits Conference, Digest of Technical Papers, pp. 464–65 (2016)
B. Murmann, The race for the extra decibel. IEEE Solid State Mag. summer 2015, 58–66 (2015)
E. Vittoz, Future of analog in the VLSI environment, in Proceedings International Symposium on Circuits Systems (ISCAS), pp. 1372–1375 (1990)
E. Vittoz, Low power low-voltage limitations and prospects in analog design, in Advances in Analog Circuit Design, ed. by R.J. van de Plassche (Kluwer Academic Publishers, 1995), p. 3
E. Dijkstra, O. Nys, E. Blumenkrantz, Low power oversampled A/D converters, in Advances in Analog Circuit Design, ed. by R.J. van de Plassche (Kluwer Academic Publishers, 1995), p. 89
R.H. Walden, Analog-to-digital converter survey and analysis. IEEE J. Sel. Areas Commun. 17, 539–550 (1999)
D. Giotta, P. Pessl, M. Clara, W. Klatzer, R. Gaggl, Low-power 14-bit current steering DAC for ADSL applications in 0.13 μm CMOS, in European Solid-State Circuits Conference, pp. 163–166 (2004)
P.C.S. Scholtens, M. Vertregt, A 6-b 1.6-Gsample/s flash ADC in 0.18μm CMOS using averaging termination. IEEE J. Solid State Circuits 37, 1599–1609 (2002)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2022 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this chapter
Cite this chapter
Pelgrom, M.J.M. (2022). Quantization. In: Analog-to-Digital Conversion. Springer, Cham. https://doi.org/10.1007/978-3-030-90808-9_9
Download citation
DOI: https://doi.org/10.1007/978-3-030-90808-9_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-90807-2
Online ISBN: 978-3-030-90808-9
eBook Packages: EngineeringEngineering (R0)