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Sample-and-Hold Circuits

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Analog-to-Digital Conversion

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Abstract

The sample-and-hold circuit and the track-and-hold circuit perform the sampling operation. These circuits operate at the highest signal levels and speeds, which makes their design a challenge. The trade-off between noise, speed, distortion, and power requires a careful balance to achieve the optimum performance. This chapter discusses the specific metrics for these circuits, such as pedestal step, droop time, and hold-mode feed-through. The different elements, switch, capacitor, and buffer are examined. Various architectures and often applied implementation schemes are shown.

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Notes

  1. 1.

    For convenience reasons, the switch is assumed to be implemented as an NMOS transistor, unless otherwise stated. Conduction takes place with a positive gate voltage.

  2. 2.

    In bipolar design, the equivalent is the base charge of a bipolar transistor.

  3. 3.

    Given the various non-linearities in charge splitting and when the source–drain potential is close to the onset of inversion, some distortion must be expected.

  4. 4.

    Which is an often encountered issue for many compensation of cancellation schemes.

  5. 5.

    This works obviously only if ΔR∕R0 is far below unity.

  6. 6.

    Everywhere in this type of calculations, even order terms are neglected as they disappear in differential design, moreover this keeps the math manageable.

  7. 7.

    A relation seems likely with the tales on Baron von Mŭnchhausen, who pulled himself out of the swamp by his bootstraps, and “booting” of computers.

  8. 8.

    The terminals with names “source” and “drain” and an arrow for the source lose their usual voltage relation: VD > VS.

  9. 9.

    The NMOS terminal with the arrow is called source and the other terminal drain, although in case of a switch these terms have no meaning.

  10. 10.

    In successive approximation converters, the same term is used to indicate from which side the input signal is applied. The technique in this section is used in these converters but describes something fundamentally different.

  11. 11.

    How to calculate the VT from the formula? Do not try to solve that analytically. Plug in a reasonable guess, for instance, VBS = 1 Volt, now VT=0.226 Volt. That is close enough, otherwise iterate once more.

  12. 12.

    All switch impedances are considered to be negligible compared to the transconductance of the opamp, assuming typical transconductance-type amplifier topologies in CMOS.

  13. 13.

    Note the intuitive discrepancy here: for a low vnoise, a large capacitor is better, and for a low charge noise qnoise, a small capacitance is better. The choice depends on the next processing step. For background on noise, see Sect. 3.1.5 on page 9.

  14. 14.

    The so-called noise excess factor is disputed, although some correction for the shape of the inversion layer may be applicable [16]. This book treats 1∕gm as a regular resistance thereby mildly overestimating the noise.

  15. 15.

    Rule of thumb means here that this is a good level to start the discussion, and various topologies give different results.

  16. 16.

    Bipolar junction transistors allow a much higher gain per transistor than CMOS devices.

  17. 17.

    See also [25] for an elementary discussion on distortion in analog circuits.

  18. 18.

    A bipolar circuit is described with simple equations, of course the same holds for a MOS circuit.

  19. 19.

    Contributions from higher order terms are not included.

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  1. Helmond, The Netherlands

    Marcel J. M Pelgrom

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Pelgrom, M.J.M. (2022). Sample-and-Hold Circuits. In: Analog-to-Digital Conversion. Springer, Cham. https://doi.org/10.1007/978-3-030-90808-9_8

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  • DOI: https://doi.org/10.1007/978-3-030-90808-9_8

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