Skip to main content

Comparators

  • Chapter
  • First Online:
Analog-to-Digital Conversion
  • 3746 Accesses

Abstract

Several classifications and subdivisions of Nyquist-rate analog-to-digital converters are possible. However, each analog-to-digital architecture requires one or more comparators. Therefore this chapter analyzes this building block extensively. Resistive and integrating amplification are discussed including aspects as kick-back, power, random offset, noise, and speed. The operation of the latch determines most speed parameters next to metastability. The chapter is concluded with a comparator catalog.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 54.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 69.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    paraphrasing prof. Bram Nauta.

  2. 2.

    Sometimes a very low pass filter is in feedback used to provide an input DC-level.

  3. 3.

    In this case, the two outputs are connected together and feed directly or via an attenuation network, the tail current bias voltage.

  4. 4.

    Invented by the US engineer Otto Schmitt in 1934, according to Wikipedia.

  5. 5.

    In a dynamic memory DRAM this is of course highly desired: the stored information is refreshed.

  6. 6.

    The term saturation is used to indicate that the circuit is far out of its operating point. Saturation of circuits has no relation with the operating regime of a transistor.

  7. 7.

    This voltage-delay relation can be exploited: measuring the delay is used to quantify the input voltage and create more resolution.

  8. 8.

    Prof. B. Murmann comment: the most important parameter for fighting metastability is the latency of an analog-to-digital converter. Given sufficient time between input sample and delivering an output word (= large latency) it is only a matter of organizing the conversion to limit metastability.

  9. 9.

    Given the exponential behavior, choosing another ratio will not make a lot of difference.

  10. 10.

    Sometimes unsavorily called “bleeder.”

  11. 11.

    Arm and StrongARM are registered trademarks of Advanced RISC Machines Ltd. The spelling used in this book “StrongARM” conforms to [29], although recently the spelling of the logo is changed to “arm”.

  12. 12.

    The analysis in this section follows [4, 27, 30, 31].

  13. 13.

    Literature sometimes postulates 1∕2Tint for a noise bandwidth, which explains a factor 2 difference in some equations.

  14. 14.

    In papers and in designs reviewed by this consultant.

References

  1. W-Y. Lee, L-S. Kim, An adaptive equalizer with the capacitance multiplication for displayport main link in 0.18-μm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20, 964–968 (2012)

    Google Scholar 

  2. S.-K. Shin, J.C. Rudell, D.C. Daly, C.E. Munoz, D.-Y. Chang, K. Gulati, H.-S. Lee, M.Z. Straayer, A 12-bit 200-MS/s zero-crossing-based pipelined ADC with early sub-ADC decision and output residue background calibration. IEEE J. Solid-State Circuits 49, 1366–1382 (2014)

    Article  Google Scholar 

  3. P. Nuzzo, F. De Bernardinis, P. Terreni, G. Van der Plas, Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans. Circuits Syst. I: Regul. Pap. 55, 1441–1454 (2008)

    Article  MathSciNet  Google Scholar 

  4. B. Razavi, The strongARM latch [a circuit for all seasons]. IEEE Solid-State Circuits Mag. 7, 12–17 (2015)

    Google Scholar 

  5. J.P. Keane et al., An 8 GS/s time-interleaved SAR ADC with unresolved decision detection achieving − 58 dBFS noise and 4 GHz bandwidth in 28 nm CMOS, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers (2017), pp. 284–285

    Google Scholar 

  6. S.-H. W. Chiang, H. Sun, B. Razavi, A 10-bit 800-MHz 19-mW CMOS ADC. IEEE J. Solid-State Circuits 49, 935–949 (2014)

    Article  Google Scholar 

  7. F. van der Goes, C.M. Ward, S. Astgimath, H. Yan, J. Riley, Z. Zeng, J. Mulder, S. Wang, K. Bult, A 1.5 mW 68 dB SNDR 80 MS/s 2 Interleaved Pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid-State Circuits 49, 2835–2845 (2014)

    Google Scholar 

  8. T. Sepke, P. Holloway, G. Sodini, H.S. Lee, Noise analysis of comparator-based circuits. IEEE Trans. Circuits Syst. I 56, 541–553 (2009)

    Article  MathSciNet  Google Scholar 

  9. A.T. Ramkaj, M. Strackx, M.S.J. Steyaert, F. Tavernier, A 1.25-GS/s 7-b SAR ADC with 36.4-dB SNDR at 5 GHz using switch-bootstrapping, USPC DAC and triple-tail comparator in 28-nm CMOS. IEEE J. Solid-State Circuits 53, 1889–1901 (2018)

    Google Scholar 

  10. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, A double-tail latch-type voltage sense amplifier with 18 ps setup+ hold time, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers (2007), pp. 314–315

    Google Scholar 

  11. X. Tang, L. Shen, B. Kasap, X. Yang, W. Shi, A. Mukherjee, D.Z. Pan, N. Sun, An energy-efficient comparator with dynamic floating inverter amplifier. IEEE J. Solid-State Circuits 55, 1011–1021 (2020)

    Article  Google Scholar 

  12. H.J.M. Veendrick, The behavior of flip-flops used as synchronizers and prediction of their failure rate. IEEE J. Solid-State Circuits 15, 169–176 (1980)

    Article  Google Scholar 

  13. H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P. W. Lai, A DC-to-1GHz tunable RF SD ADC achieving DR =  74 dB and BW =  150 MHz at f0 = 450 MHz using 550 mW, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers (2012), pp. 150–151

    Google Scholar 

  14. A. Shikata, R. Sekimoto, T. Kuroda, H. Ishikuro, A 0.5 V 1.1 MS/s 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS. IEEE J. Solid-State Circuits 47, 1022–1030 (2012)

    Google Scholar 

  15. Y. Yoon, N. Sun, A 6-bit 0.81-mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration. IEEE J. Solid-State Circuits 53, 789–798 (2018)

    Google Scholar 

  16. Y. Duan, E. Alon, A 6b 46 GS/s ADC with > 23 GHz BW and sparkle-code error correction, in IEEE Symp. VLSI Circuits Dig. Tech. Papers (2015), pp. C162–C163

    Google Scholar 

  17. A. Nikoozadeh, B. Murmann, An analysis of latch comparator offset due to load capacitor mismatch. IEEE Trans. Circuits Syst. II Exp. Briefs 53, 1398–1402 (2006)

    Article  Google Scholar 

  18. H.L. Fiedler, B. Hoefflinger, W. Demmer, P. Draheim, A 5-bit building block for 20 MHz A/D converters. IEEE J. Solid-State Circuits 26, 151–155 (1981)

    Article  Google Scholar 

  19. B.-S. Song, S.-H. Lee, M.F.A Tompsett, 10-b 15-MHz CMOS recycling two-step A/D converter. IEEE J. Solid-State Circuits 25, 1328–1338 (1990)

    Google Scholar 

  20. S.-W.M. Chen, R.W. Brodersen, A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS. IEEE J. Solid-State Circuits 41, 2669–2680 (2006)

    Google Scholar 

  21. B. Nauta, A.G.W. Venes, A 70 MS/s 110 mW 8-b CMOS folding and interpolating A/D converter. IEEE J. Solid-State Circuits 30, 1302–1308 (1995)

    Article  Google Scholar 

  22. A.G.W. Venes, R.J. van de Plassche, An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing. IEEE J. Solid-State Circuits 31, 1846–1853 (1996)

    Article  Google Scholar 

  23. G. Yin, F. Op’t Eynde, W. Sansen, A high-speed CMOS comparator with 8-b resolution. IEEE J. Solid-State Circuits 27, 208–211 (1992)

    Article  Google Scholar 

  24. J.-T. Wu, B.A. Wooley, A 100-MHz pipelined CMOS comparator. IEEE J. Solid-State Circuits 23, 1379–1385 (1988)

    Article  Google Scholar 

  25. S. Limotyrakis, S.D. Kulchycki, D.K. Su, B.A. Wooley, A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE J. Solid-State Circuits 40, 1057–1067 (2005)

    Article  Google Scholar 

  26. Shen et al., A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS. IEEE J. Solid-State Circuits 53, 1149–1159 (2018)

    Google Scholar 

  27. A. Ramkaj, Multi-GHz Bandwidth Power-efficient Nyquist A/D conversion, Ph.D. Thesis, KU Leuven, March 2021

    Google Scholar 

  28. T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J. Solid-State Circuits 28, 523–527 (1993)

    Article  Google Scholar 

  29. J. Montanaro et al., A 160 MHz, 32b, 0.5W CMOS RISC microprocessor. IEEE J. Solid-State Circuits 31, 1703–1714 (1996)

    Google Scholar 

  30. B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid-State Circuits 39, 1148–1158 (2004)

    Article  Google Scholar 

  31. A.T. Ramkaj, M.S. Steyaert, F. Tavernier, A 13.5-Gb/s 5-mV sensitivity 26.8-ps clk-out delay triple-latch feedforward dynamic comparator in 28-nm CMOS. Solid-State Circuits Lett. 2, 167–170 (2019) (ESSCIRC2019 reprint)

    Google Scholar 

  32. K-L.J. Wong, C-K.K. Yang, Offset compensation in comparators with minimum input-referred supply noise. IEEE J. Solid-State Circuits 37, 837–840 (2004)

    Google Scholar 

  33. B. Razavi, The design of a comparator [the analog mind]. IEEE Solid-State Circuits Mag. 12, 8–14 (2020)

    Google Scholar 

  34. W. Ellersick, K.Y. Chih-Kong, M. Horowitz, W. Dally, GAD: a 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link, in Symposium on VLSI Circuits, Digest of Technical Papers (1999), pp. 49–52

    Google Scholar 

  35. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, G. Van der Plas, A 2.2mW 5b 1.75GS/s folding flash ADC in 90 nm digital CMOS, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers (2008), pp. 252–611

    Google Scholar 

  36. Y.-S. Shu, A 6b 3GS/s 11mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators, in Symposium on VLSI Circuits Digest of Technical Papers (2012), pp. 26–27

    Google Scholar 

  37. I.-M. Yi, N. Miura, H. Fukuyama, H. Nosaka, A 15.1-mW 6-GS/s 6-bit single-channel flash ADC with selectively activated 8x time- domain latch interpolation. IEEE J. Solid-State Circuits 56, 455–464 (2021)

    Google Scholar 

  38. B. Goll, H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans. Circuits Syst. II: Exp. Briefs 56, 810–814 (2009)

    Google Scholar 

  39. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s. IEEE J. Solid-State Circuits 45, 1007–1015 (2010)

    Google Scholar 

  40. H.S. Bindra, C.E. Lokin, D. Schinkel, A.-J. Annema, B. Nauta, A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise. IEEE J. Solid-State Circuits 53, 1902–1912 (2018)

    Google Scholar 

  41. N. Fukushima, T. Yamada, N. Kumazawa, Y. Hasegawa, M. Soneda, A CMOS 40 MHz 8b 105 mW two-step ADC, in International Solid-State Circuits Conference, Digest of Technical Papers (1989), pp. 14–15

    Google Scholar 

  42. J.H. Atherton, H.T. Simmonds, An offset reduction technique for use with CMOS integrated comparators and amplifiers. IEEE J. Solid-State Circuits 27, 1168–1175 (1992)

    Article  Google Scholar 

  43. M. Haas, D. Draxelmayr, F. Kuttner, B. Zojer, A monolithic triple 8-bit CMOS video coder. IEEE Trans. Consum. Electron. 36, 722–729 (1990)

    Article  Google Scholar 

  44. V.H.-C. Chen, L. Pileggi, A 69.5 mW 20 GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32 nm CMOS SOI. IEEE J. Solid-State Circuits 49, 2891–2901 (2014)

    Google Scholar 

  45. A. Varzaghani et al., A 10.3-GS/s, 6-bit flash ADC for 10 G ethernet applications. IEEE J. Solid-State Circuits 48(8), 3038–3048 (2013)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2022 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Pelgrom, M.J.M. (2022). Comparators. In: Analog-to-Digital Conversion. Springer, Cham. https://doi.org/10.1007/978-3-030-90808-9_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-90808-9_12

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-90807-2

  • Online ISBN: 978-3-030-90808-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics