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Specification and Runtime Verification of Temporal Assessments in Simulink

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Runtime Verification (RV 2021)


Formalization of specifications is a key step towards rigorous system design of complex engineered systems such as cyber-physical systems. Temporal logics are a suitable expressive formalism for capturing temporal specifications. However, since engineers and practitioners are often unfamiliar with the symbols and vocabulary of temporal logic, informal natural-language specifications still are used abundantly in practice. This tool paper presents the Temporal Assessments feature in Simulink\(^{\tiny {\textregistered }}\) Test\(^{\tiny {\text {TM}}}\) that strives to achieve the best of both worlds. It provides graphical user interfaces and visual examples for users to interactively create temporal specifications without the need to author logical formulae by hand, yet any user-authored temporal assessment is a valid logical formula in an internal representation. Iterative folding of clauses enables the specification to be presented to read like English language sentences. Key highlights of the feature along with examples of authoring and runtime verification of temporal logic specifications are presented.

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Contributions by Dr. Jean-François Kempf and Dr. Khoo Yit Phang to an earlier extended abstract on this topic are gratefully acknowledged.

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Correspondence to Akshay Rajhans .

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Rajhans, A., Mavrommati, A., Mosterman, P.J., Valenti, R.G. (2021). Specification and Runtime Verification of Temporal Assessments in Simulink. In: Feng, L., Fisman, D. (eds) Runtime Verification. RV 2021. Lecture Notes in Computer Science(), vol 12974. Springer, Cham.

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-88493-2

  • Online ISBN: 978-3-030-88494-9

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