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Automated Verification of Temporal Properties of Ladder Programs

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Part of the Lecture Notes in Computer Science book series (LNPSE,volume 12863)


Programmable Logic Controllers (PLCs) are industrial digital computers used as automation controllers in manufacturing processes. The Ladder language is a programming language used to develop PLC software. Our aim is to prove that a given Ladder program conforms to an expected temporal behaviour given as a timing chart, describing scenarios of execution. We translate the Ladder code and the timing chart into a program for the Why3 environment, within which the verification proceeds by generating verification conditions, to be checked valid using automated theorem provers. The ultimate goal is two-fold: first, by obtaining a complete proof, we can verify the conformance of the Ladder code with respect to the timing chart with a high degree of confidence. Second, when the proof is not fully completed, we obtain a counterexample, illustrating a possible execution scenario of the Ladder code which does not conform to the timing chart.


  • Ladder language for programming
  • PLCs
  • Timing charts
  • Formal specification
  • Deductive verification
  • Why3 environment

This work has been partially supported by the bilateral contract ProofInUse-MERCE between Inria team Toccata and Mitsubishi Electric R&D Centre Europe, Rennes.

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  • DOI: 10.1007/978-3-030-85248-1_2
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    There are no do-while loops in WhyML, we just mean by do-while style loop a code piece of the following form with two occurrences of the loop body: “ ”.


  1. Baudin, L.: Deductive verification with the help of abstract interpretation. Technical report, Université Paris-Saclay, November 2017.

  2. Baudin, P., et al.: ACSL: ANSI/ISO C specification language, version 1.16 (2020).

  3. Becker, B., Belo Lourenço, C., Marché, C.: Explaining counterexamples with giant-step assertion checking. In: Creissac Campos, J., Paskevich, A. (eds.) 6th Workshop on Formal Integrated Development Environments (F-IDE 2021). Electronic Proceedings in Theoretical Computer Science, May 2021.

  4. Belo Lourenço, C., Cousineau, D., Faissole, F., Marché, C., Mentré, D., Inoue, H.: Formal analysis of Ladder programs using deductive verification. Research Report RR-9402, Inria, April 2021.

  5. Biallas, S., Kowalewski, S., Stattelmann, S., Schlich, B.: Efficient handling of states in abstract interpretation of industrial programmable logic controller code. In: Proceedings of the 12th International Workshop on Discrete Event Systems, pp. 400–405. IFAC, Cachan, France (2014)

    Google Scholar 

  6. Bobot, F., Filliâtre, J.C., Marché, C., Paskevich, A.: Let’s verify this with Why3. Int. J. Softw. Tools Technol. Transf. (STTT) 17(6), 709–727 (2015). DOI:

    CrossRef  Google Scholar 

  7. Cousineau, D., Mentré, D., Inoue, H.: Automated deductive verification for ladder programming. In: Monahan, R., Prevosto, V., Proença, J. (eds.) Proceedings of the Fifth Workshop on Formal Integrated Development Environment, F-IDE@FM 2019, Porto, Portugal, 7th October 2019. Electronic Proceedings in Theoretical Computer Science, vol. 310, pp. 7–12 (2019).

  8. Dailler, S., Hauzar, D., Marché, C., Moy, Y.: Instrumenting a weakest precondition calculus for counterexample generation. J. Log. Algebraic Methods Program. 99, 97–113 (2018).

    MathSciNet  CrossRef  MATH  Google Scholar 

  9. Darvas, D., Majzik, I., Blanco Viñuela, E.: Formal verification of safety plc based control software. In: Ábrahám, E., Huisman, M. (eds.) Integrated Formal Methods. Lecture Notes in Computer Science, vol. 9681, pp. 508–522. Springer (2016).

    CrossRef  Google Scholar 

  10. De Oliveira, S., Prévosto, V., Bardin, S.: Au temps en emporte le C. In: Baelde, D., Alglave, J. (eds.) Vingt-sixièmes Journées Francophones des Langages Applicatifs (JFLA 2015) (2015).

  11. Drath, R., Luder, A., Peschke, J., Hundt, L.: AutomationML - the glue for seamless automation engineering. In: ETFA - IEEE International Conference on Emerging Technologies and Factory Automation, pp. 616–623 (2008).

  12. Fehnker, A., Huuck, R., Schlich, B., Tapp, M.: Automatic bug detection in microcontroller software by static program analysis. In: Nielsen, M., Kučera, A., Miltersen, P.B., Palamidessi, C., Tůma, P., Valencia, F. (eds.) Theory and Practice of Computer Science (SOFSEM). Lecture Notes in Computer Science, vol. 5404, pp. 267–278. (2009).

    CrossRef  Google Scholar 

  13. Jeannet, B., Miné, A.: Apron: A library of numerical abstract domains for static analysis. In: Bouajjani, A., Maler, O. (eds.) Computer Aided Verification. pp. 661–667. Springer (2009)

    CrossRef  Google Scholar 

  14. Mitsubishi Electric Corporation: Mitsubishi programmable controllers training manual – MELSEC iQ-R Series basic course (for GX Works3). (2016). Accessed 30 March 2021

  15. Nguyen, T., Aoki, T., Tomita, T., Endo, J.: Integrating static program analysis tools for verifying cautions of microcontroller. In: Asia-Pacific Software Engineering Conference (APSEC), pp. 86–93 (2019).

  16. Ovatman, T., Aral, A., Polat, D., Ünver, A.: An overview of model checking practices on verification of PLC software. Softw. Syst. Model. 15, 1–24 (12 2014).

    CrossRef  Google Scholar 

  17. Ramanathan, R.: The IEC 61131–3 programming languages features for industrial control systems. In: World Automation Congress (WAC), pp. 598–603 (2014).

  18. Roques, A.: PlantUML standard library. (2009). Accessed 24 March 2021

  19. Stouls, N., Groslambert, J.: Vérification de propriétés LTL sur des programmes C par génération d’annotations. Research report (2011).

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Correspondence to Claude Marché .

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Lourenço, C.B., Cousineau, D., Faissole, F., Marché, C., Mentré, D., Inoue, H. (2021). Automated Verification of Temporal Properties of Ladder Programs. In: Lluch Lafuente, A., Mavridou, A. (eds) Formal Methods for Industrial Critical Systems. FMICS 2021. Lecture Notes in Computer Science(), vol 12863. Springer, Cham.

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