Abstract
Dynamic binary translation (DBT) transforms machine code at runtime into an optimzed form. DBT can have cross platform compatibility, better energy efficiency or improved performance as its goals. The goal of this work is to improve performance by executing perfomance critical parts of the binary code on a Coarse Grained Reconfigurable Array (CGRA). We show how the CGRA is integrated into the system and explain how performance critical parts of the binary code can be identified. We demonstrate the feasibility of a dynamic binary translation from RISC-V ISA to a CGRA, give details about the employed optimizations and show that the performance of a whole benchmark set can be improved by a factor of 1.7 without the need for any user intervention.
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Wirsch, R., Hochberger, C. (2021). Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA. In: Hochberger, C., Bauer, L., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2021. Lecture Notes in Computer Science(), vol 12800. Springer, Cham. https://doi.org/10.1007/978-3-030-81682-7_8
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