DRAM-Based Processor for Deep Neural Networks Without SRAM Cache

Abstract

Modern computing architectures use cache memory as the buffer between high speed computing units and low latency main memory. Higher capacity caches are thought to be critical for deep neural network processors, which handle large amounts of data. However, as cache memory capacity increases, it occupies large die area that can otherwise be used for computing units. This is the inherent trade off between memory capacity and performance. In this work, we present a deep neural network processing chip, with a near-memory computing architecture. We eliminate the SRAM cache and use DRAM only as on-chip memory, delivering high performance and high memory capacity.