Abstract
The computing potential of programmable switches with multi-Tbit/s throughput is of increasing interest to the research community and industry alike. Such systems have already been employed in a wide spectrum of applications, including statistics gathering, in-network consensus protocols, or application data caching. Despite their high throughput, most architectures for programmable switches have practical limitations, e.g., with regard to stateful operations.
FPGAs, on the other hand, can be used to flexibly realize switch architectures for far more complex processing operations. Recently, FPGAs have become available that feature 3D-memory, such as HBM stacks, that is tightly integrated with their logic element fabrics. In this paper, we examine the impact of exploiting such HBM to accelerate an inter-server join operation at the switch-level between the servers of a distributed database system. As the hash-join algorithm used for high performance needs to maintain a large state, it would overtax the capabilities of conventional software-programmable switches.
The paper shows that across eight 10G Ethernet ports, the single HBM-FPGA in our prototype can not only keep up with the demands of over 60 Gbit/s of network throughput, but it also beats distributed-join implementations that do not exploit in-network processing.
This work was partially funded by the DFG Collaborative Research Center 1053 (MAKI) and by the German Federal Ministry for Education and Research (BMBF) with the funding ID 16ES0999. The authors would like to thank Xilinx Inc. for supporting their work by donations of hard- and software.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Blanas, S., Li, Y., Patel, J.M.: Design and evaluation of main memory hash join algorithms for multi-core CPUs. In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2011, Athens, Greece, 12–16 June 2011, pp. 37–48. ACM (2011)
Blöcher, M., Ziegler, T., Binnig, C., Eugster, P.: Boosting scalable data analytics with modern programmable networks. In: Proceedings of the 14th International Workshop on Data Management on New Hardware. DAMON 2018. Association for Computing Machinery, New York (2018)
DeWitt, D.J., Katz, R.H., et al.: Implementation techniques for main memory database systems. SIGMOD Rec. 14(2), 1–8 (1984)
Dreseler, M., Boissier, M., Rabl, T., Uflacker, M.: Quantifying TPC-H choke points and their optimizations. Proc. VLDB Endow. 13(8), 1206–1220 (2020)
Firestone, D., Putnam, A., et al.: Azure accelerated networking: Smartnics in the public cloud. In: Proceedings of the 15th USENIX Conference on Networked Systems Design and Implementation, NSDI 2018, pp. 51–64. USENIX Association, USA (2018)
Gustavo, A., Binnig, C., et al.: DPI: the data processing interface for modern networks. In: Proceedings of CIDR 2019 (2019)
Heinz, C., Hofmann, J., Korinth, J., Sommer, L., Weber, L., Koch, A.: The TaPaSCo open-source toolflow. J. Signal Process. Syst. 93, 1–19 (2021). https://doi.org/10.1007/s11265-021-01640-8
Hofmann, J., Thostrup, L., Ziegler, T., Binnig, C., Koch, A.: High-performance in-network data processing. In: International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2019, Los Angeles, United States (2019)
Kimball, R., Ross, M.: The Data Warehouse Toolkit: The Complete Guide to Dimensional Modeling, 2nd edn. Wiley, Hoboken (2002)
Preshing, J.: Hash collision probabilities (2011). https://preshing.com/20110504/hash-collision-probabilities/
Rödiger, W., Mühlbauer, T., Kemper, A., Neumann, T.: High-speed query processing over high-speed networks. Proc. VLDB Endow. 9(4), 228–239 (2015)
Sapio, A., Abdelaziz, I., et al.: In-network computation is a dumb idea whose time has come. In: Proceedings of the 16th ACM Workshop on Hot Topics in Networks, pp. 150–156. HotNets-XVI, Association for Computing Machinery, New York (2017)
Wellons, C.: Hash function prospector (2020). https://github.com/skeeto/hash-prospector
Zilberman, N., Audzevich, Y., Covington, G.A., Moore, A.W.: NetFPGA SUME: toward 100 Gbps as research commodity. IEEE Micro 34(5), 32–41 (2014)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this paper
Cite this paper
Wirth, J., Hofmann, J.A., Thostrup, L., Koch, A., Binnig, C. (2021). Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_2
Download citation
DOI: https://doi.org/10.1007/978-3-030-79025-7_2
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-79024-0
Online ISBN: 978-3-030-79025-7
eBook Packages: Computer ScienceComputer Science (R0)