Abstract
The von Neumann architecture equips us with an understanding how a computer processes our program code step by step. Our brief review of the architecture highlights the role of registers for our numerical computations. We will augment the straightforward definition of a register later to realise vector processing, i.e. the first flavour of hardware parallelism, while the architecture review provides clues why many numerical codes struggle with performance flaws and bottlenecks on our CPUs.
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Notes
- 1.
The fact that we do not distinguish code and instructions within the memory—they are technically both just number sequences and the software has to interpret them either as data or instruction codes—is a built-in security problem. Malware can alter code by pretending it wrote data into the memory.
- 2.
This is where the machine truncates the bit sequence of the floating point number into the IEEE format (cmp. Sect. 4.2.3): If the ALU uses 80 bits per double internally for example, the number is now reduced to 64.
- 3.
This is the price to pay for fame: the most important technological achievements might be named after you, but then the flaws tied to it inherit your name, too.
- 4.
With a theoretical computer science background, you will characterise algorithms as \(\mathcal {O}(n)\) or \(\mathcal {O}(n\log n)\) or ...where n counts the algorithm’s operations. In reality, there might be an additional \(\mathcal {O}(m)\), \(\mathcal {O}(m \log m)\), ...term paraphrasing the memory movement cost. It is not clear a priori which term dominates the actual runtime.
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Weinzierl, T. (2021). A Simplistic Machine Model. In: Principles of Parallel Scientific Computing. Undergraduate Topics in Computer Science. Springer, Cham. https://doi.org/10.1007/978-3-030-76194-3_5
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DOI: https://doi.org/10.1007/978-3-030-76194-3_5
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