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FinFET Technology

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Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

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Abstract

This chapter begins by presenting the challenges imposed by technology scaling and justifying the need for new devices for ensuring the microelectronics advancement of sub-22nm nodes. FinFET devices were pointed out as the best candidate to maintain the technology scaling. Then, this chapter presents the main parameters, configurations, and properties of these devices. Then, this chapter discusses the semiconductor industrys advancement, highlighting the main achievements until now and the trends for the coming years. The next step is dedicated to presenting the layout issues for designs using FinFET technologies, showing the main differences of the planar node layouts. Finally, this chapter also details some characteristics of sub-22nm predictive models and process design kits available for academic use.

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Authors and Affiliations

  1. Universidade Católica de Pelotas, Pelotas, Rio Grande do Sul, Brazil

    Alexandra Zimpeck

  2. Universidade Federal de Santa Catarina, Florianópolis, Santa Catarina, Brazil

    Cristina Meinhardt

  3. ONERA/DPHY University of Toulouse, Toulouse, France

    Laurent Artola

  4. Inst de Informatica, Bloco IV, CP15064, Univ Federal do Rio Grande do Sul, Porto Alegre, Rio Grande do Sul, Brazil

    Ricardo Reis

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  4. Ricardo Reis
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Zimpeck, A., Meinhardt, C., Artola, L., Reis, R. (2021). FinFET Technology. In: Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs. Springer, Cham. https://doi.org/10.1007/978-3-030-68368-9_2

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