Architecture for Silicon-Based Implementation of Regularized Fast Hartley Transform

Abstract

This chapter introduces a computing architecture, based upon the use of a single processing element, for resource-efficient, scalable and device-independent solutions for the parallel computation of the regularized FHT. The solutions exploit partitioned memory for the storage of both data and trigonometric coefficients and seek to maximize the computational density when implemented with silicon-based parallel computing equipment. A pipelined implementation of the generic double butterfly is discussed which exploits SIMD processing within each stage of the computational pipeline and conflict-free parallel memory addressing schemes for both data and trigonometric coefficients. These features lead to an approximate figure of $\raisebox{1ex}{$N$}\!\left/ \!\raisebox{-1ex}{$P$}\right..{\log}_4N$ clock cycles for the latency of the regularized FHT, this achieved after taking into account the level of parallelism, P, as introduced via the adoption of the partitioned data memory. Four versions of the PE are discussed that are each a simple variation of the same basic design and each compatible with the single-PE recursive computing architecture, enabling trade-offs to be made of the arithmetic and memory requirements against addressing complexity. An FPGA implementation of the regularized FHT is then discussed and its performance compared with two commercially available FFT solutions. The chapter concludes with a discussion of the results obtained.