Abstract
Despite the success of formal verification methods in the last 20 years, the proof of correctness of arithmetic hardware blocks involving multiplication still drives the verification tools into their limits. At the moment, the most promising methods for verification are based on Symbolic Computer Algebra (SCA), and they have shown very good results even for large and architecturally complex multipliers. To allow the community a broad comparison when verifying different multiplier architectures, open, configurable, and scalable multiplier benchmarks are needed.
In this chapter, we present the multiplier generator GenMul, which outputs multiplier circuits in Verilog. The input size of a multiplier and each multiplier stage can be configured with GenMul. In addition, GenMul is open source under MIT-license to ease for adding new architectures. Overall, this allows to challenge formal methods as shown by experiments which compare recent verification approaches.
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Notes
- 1.
Bryant already proved in his seminal paper introducing BDDs [1] that the Boolean function for the middle output bit of the binary multiplication function has only exponential BDD representations.
- 2.
Word-level Decision Diagrams represent integer-valued functions \(f : \{0, 1\}^n \rightarrow \mathbb {Z}\). Many different types of Word-level Decision Diagrams have been introduced, e.g., MTBDDs, EVBDDs, BMDs, *BMDs, K*BMDs, and *PHDDs [2]. BMDs, *BMDs, K*BMDs, and *PHDDs have the advantage that they provide efficient representations for the multiplier function \(mult : \{0, 1\}^{2n} \rightarrow \mathbb {Z}\) mapping two n-bit operand vectors to the number representing the product of the two operands. Although there are papers proposing an efficient construction of Word-level Decision Diagrams from multiplier circuits by a so-called backward construction that starts from a Word-level decision diagram representing the “output word” \(\sum _{i=0}^{2n -1} z_i 2^i\) and performs substitutions of gate functions in reverse topological order [3, 4], even intensive efforts could not confirm any practical success of this approach for non-trivial multipliers.
- 3.
GenMul is available on http://www.sca-verification.org/genmul.
- 4.
In literature sometimes also termed significance.
- 5.
For this chapter we only used 40 bits per multiplier input, since this already shows the challenges. In [20] we report results for benchmarks generated with GenMul for up to 512 × 512 multipliers.
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Acknowledgements
This work was supported by the German Research Foundation (DFG) within the project VerA (GR 3104/6-1 and DR 297/37-1).
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Appendix
Appendix
GenMulWebsite
GenMul is now available on http://www.sca-verification.org/genmul. In Fig. 3, a screenshot of the GenMul website is shown.
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Mahzoon, A., Große, D., Drechsler, R. (2021). GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools. In: Drechsler, R., Große, D. (eds) Recent Findings in Boolean Techniques. Springer, Cham. https://doi.org/10.1007/978-3-030-68071-8_9
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