Abstract
Digital system simulation on the architecture level is considered, i.e. instruction set and internal register changes emulation. Emulators is used for embedded software debugging and in the design process of new special processor development. The requirements for emulators is formalized. There is the classification of debugging features of emulators and possible ways of debugging mode implementation. The structure of emulators is described. Graph model of emulator structure is proposed. Each instruction is presented as the sequence of smaller operations. If different instructions include the same operations, such operations could be fulfilled by the same program modules. Those modules could be included into all appropriate instruction simulation parts of emulator, or emulator could include only one copy of each operation program module, and the module could be called while executing the appropriate instruction. The emulator structure determination is formalized as an extreme task. Practical methodology for emulator structure determination is proposed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Zhou, J., Zhang, Z., Xie, P., Wang, J.: A test data generation approach for automotive software. In: 2015 IEEE International Conference on Software Quality, Reliability and Security – Companion, Vancouver, BC, pp. 216–220 (2015)
Emelenko, A.N., Mallachiev, K.A., Pakulin, N.V.: Debugger for real-time OS: challenges of multiplatform support. Trudi Instituta systemnogo programmirovaniya RAN 29(4), 295–302 (2017)
Uetsuki, K., Tsuda, K., Matsuodani, T.: Automated compatibility testing method for software logic by using symbolic execution. In: IEEE Eighth International Conference on Software Testing, Verification and Validation Workshops (ICSTW), Graz, pp. 1–6. IEEE (2015)
Yu, H., Song, H., Xiaoming, L., Xiushan, Y.: Using symbolic execution in embedded software testing. In: 2008 International Conference on Computer Science and Software Engineering, Hubei, pp. 738–742. IEEE (2008)
Suresh, V.P., Chakrabarti, S.K., Jetley, R., Mohan, D.: Handling backtracking for symbolic testing of embedded software. In: 2019 24th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Zaragoza, Spain, pp. 1445–1448 (2019)
Zhang, C., et al.: SmartUnit: empirical evaluations for automated unit testing of embedded software in industry. In: 2018 IEEE/ACM 40th International Conference on Software Engineering: Software Engineering in Practice Track (ICSE-SEIP), Gothenburg, pp. 296–305 (2018)
Ohbayashi, H., Kanuka, H., Okamoto, C.: A preprocessing method of test input generation by symbolic execution for enterprise application. In: 2018 25th Asia-Pacific Software Engineering Conference (APSEC), Nara, Japan (2018)
Lambert, J.E., Halsall, F.: Program debugging and performance evaluation aids for a multi-microprocessor development system. Software Microsyst. 3(1), 100–105 (1984)
H. Yuan, H., Yao, Y., He, P.: An emulation and context reconstruction tool for embedded high-precision positioning system. In: 2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Daegu, pp. 107–107 (2016)
Salim, A.J., Salim, S.I.M., Samsudin N.R., Soo, Y.: Customized instruction set simulation for soft-core RISC processor. In: 2012 IEEE Control and System Graduate Research Colloquium, Shah Alam, Selangor, pp. 38–42. IEEE (2012)
Prathyusha, M., Kumar, C.V.R.: A survey paper on debugging tools and frameworks for debugging real time industrial problems and scenerios. In: 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN), Vellore, India, pp. 1–4 (2019)
Liang, X.: Computer architecture simulators for different instruction formats. In: 2019 International Conference on Computational Science and Computational Intelligence (CSCI), Las Vegas, NV, USA, pp. 806–811. IEEE (2019)
Braun, G., Nohl, A., Hoffmann, A., Schliebusch, O., Leupers, R., Meyr, H.: A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 23(12), 1625–1639 (2004)
Garcia, M., Francesquini, E., Azevedo, R., Rigo, S.: HybridVerifier: a cross-platform verification framework for instruction set simulators. IEEE Embedded Syst. Lett. 9(2), 25–28 (2017)
Zhang, Z., Hu, X., Shi, L.: High-performance instruction-set simulator for TMS320C62x DSP. In: 2010 The 2nd International Conference on Industrial Mechatronics and Automation, Wuhan, pp. 517–520. IEEE (2010)
Mueller-Gritschneder, D., Dittrich, M., Greim, M., Devarajegowda, K., Ecker. W., Schlichtmann, U.: The Extendable Translating Instruction Set Simulator (ETISS) Interlinked with an MDA Framework for Fast RISC Prototyping. In: 2017 International Symposium on Rapid System Prototyping (RSP), pp. 79–84. IEEE. Seoul (2017)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Ivannikov, A. (2021). Emulators – Digital System Simulation on the Architecture Level. In: Dolinina, O., et al. Recent Research in Control Engineering and Decision Making. ICIT 2020. Studies in Systems, Decision and Control, vol 337. Springer, Cham. https://doi.org/10.1007/978-3-030-65283-8_18
Download citation
DOI: https://doi.org/10.1007/978-3-030-65283-8_18
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-65282-1
Online ISBN: 978-3-030-65283-8
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)