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Analog IP Protection and Evaluation

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Emerging Topics in Hardware Security

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Abstract

The increasing cost of manufacturing integrated circuits (IC) has forced many companies to go fabless. With the outsourcing of IC fabrication in a globalized/distributed design flow, including multiple (potentially untrusted) entities, the semiconductor industry faces several challenging security threats. This fragility in the face of weak state-of-the-art intellectual property (IP) protection has resulted in hardware security vulnerabilities, such as IP piracy, overbuilding, reverse engineering, and hardware Trojans. To address these issues at the hardware level, different design-for-trust (DfTr) techniques, such as IC metering, watermarking, IC camouflaging, split manufacturing, and logic locking have been proposed to secure digital circuits. Though there are many DfTr techniques to secure digital circuits, there is a great dearth of techniques for analog and mixed-signal (AMS) IP protection. However, analog ICs are more prone to supply-chain attacks than digital ICs as they are easier to reverse engineer. This high vulnerability is due to their low transistor count compared to their digital counterparts. To address the impact of process variations, they also have predefined layout patterns, e.g., common-centroid. Analog ICs are not simple, although they have less number of transistors. Even with only hundreds of transistors, analog IC design requires highly experienced designers and a long time, as analog behaviors are quite complicated.

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Acknowledgements

This work is funded by the National Science Foundation C(CF-1815583, CNS-1618824, CNS-1828840, STARSS-1618797, and SATC CAREER-1822848), Semiconductor Research Corporation (2016-T3S-2688 and 2016-T3S-2689), and Intel. The authors thank Qualcomm and Synopsys for their support in this work.

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  1. Texas A&M University, College Station, TX, USA

    N. G. Jayasankaran, A. Sanabria-Borbón, E. Sánchez-Sinencio, J. Hu & J. Rajendran

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  1. N. G. Jayasankaran
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  2. A. Sanabria-Borbón
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Correspondence to J. Rajendran .

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  1. University of Florida, Gainesville, FL, USA

    Mark Tehranipoor

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Jayasankaran, N.G., Sanabria-Borbón, A., Sánchez-Sinencio, E., Hu, J., Rajendran, J. (2021). Analog IP Protection and Evaluation. In: Tehranipoor, M. (eds) Emerging Topics in Hardware Security . Springer, Cham. https://doi.org/10.1007/978-3-030-64448-2_16

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  • DOI: https://doi.org/10.1007/978-3-030-64448-2_16

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