Abstract
The quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LCoscillators, or a very compact area by relying on ringoscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ringoscillator, that have the potential to break this tradeoff. After analyzing their jitterpower product, the conditions that ensure optimum performance are derived and a novel digitaltotime converter rangereduction technique is introduced, to enable lowjitter and lowpower fractionalN frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm\(^{2}\) and covers the 1:6to3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHzto30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitterpower figureofmerit of −244 dB in the fractionalN mode, the prototype outperforms prior stateoftheart inductorless frequency synthesizers.
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1 Introduction
The roaring demand for wireless connectivity at a low price point has, in recent years, spurred the interest for highlyintegrated transceiver solutions that are able to cut down on expensive silicon area requirements. In this context, one of the major limiting factors is generally represented by the frequency synthesizer used to generate the local oscillator signal for the transceiver. Conventionally implemented as phaselocked loops (PLLs) based around LCoscillators, they require large amounts of area due to the use of integrated inductors. Ringoscillator (RO) based frequency synthesizers, on the other hand, ensure reduced area occupation, provide an inherent immunity to magnetic pulling and are better suited to scaling. However, they also suffer from a worse power vs. phase noise tradeoff with respect to their LCbased counterparts [1], which—leading to an undesirable degradation in the overall transceiver efficiency—prevents a more widespread adoption.
An effective way to overcome this issue, for applications that require very low integrated jitter levels but are not constrained by tight spotnoise requirements (e.g. IEEE 802.11b and highperformance clocking), is to perform an aggressive highpass filtering of the RO phase noise. In principle, this could be achieved by increasing the bandwidth of the phaselocked loop (PLL) controlling the RO. In practice, however, the PLL bandwidth cannot be increased indefinitely, as it must remain well below the reference frequency to ensure stability [2]. The achievable level of filtering is therefore generally rather limited.
To increase the ringoscillator phase noise filtering bandwidth beyond the limits set by conventional PLLs, two architectures have been proposed: multiplying delaylocked loops (MDLLs) [3,4,5,6,7,8,9,10] and injectionlocked phaselocked loops (ILPLLs) [11,12,13,14,15,16,17,18,19,20]. Both architectures suppress jitter accumulation by performing a periodic realignment of the ring oscillator edges to a cleaner reference signal edge. Whereas in the ILPLL case this is achieved by enforcing the crossing times of the output signal through switch transistors—which only allow for partial realignment—MDLLs rely on a multiplexer (MUX) placed within the RO loop to fully substitute a recirculating edge with the cleaner reference one (Fig. 4.1). Since this effectively limits jitter accumulation in the RO to only one reference cycle, MDLLs are able to achieve the highest filtering bandwidth among the two architectures, at about half of the reference frequency, \(f_{ref}/2\) [21]. As a result, they clearly represent the architecture of choice for highlyefficient inductorless frequency synthesizers.
2 FractionalN MDLLs
The basic MDLL architecture introduced in the previous section, inherently requires that the output frequency be an integer multiple of the input one, so that precise edge substitution can be achieved. However, to provide a viable alternative to conventional LCbased PLLs, MDLLs should also be able to generate output frequencies that are not an integer multiple of the reference one—a concept commonly referred to as fractional frequency synthesis. Unfortunately, extending the MDLL architecture to fractionalN operation presents some extra challenges.
The conventional approach to enable fractionalN frequency synthesis in MDLLs [8], is illustrated in Fig. 4.2. Similarly to a PLL, the modulus control, MC[k], of the feedback divider is dithered by a \(\Delta \Sigma \) modulator to achieve an average fractional division factor. For the simpler case of a firstorder modulator, MC[k] is switched between two levels, N and \(N+1\). This, in turn, leads to a time error between the rising reference and oscillator edges, which follows a ramp from 0 to \(T_v\), where \(T_v\) is the oscillator period. To avoid the spectral degradation resulting from such a large quantization noise being introduced in the RO during edgereplacement, a digitaltotime converter (DTC)—which is an element that allows to introduce a digitallycontrolled delay on a signal—is placed on the reference path, to realign the injected edges to the recirculating RO edges. The control signal for the DTC, del[k], is derived by first accumulating the \(\Delta \Sigma \)quantization error to account for the intrinsic frequencytophase integration in the MMD, and then scaling it by a proper gain so as to match the DTC’s bittotime conversion gain. As a result, the required DTC range is set by the amplitude of the \(\Delta \Sigma \) quantization error being canceled.
Unfortunately, the DTC also degrades the reference signal by introducing both random as well as deterministic jitter, due to component noise and nonlinearities in its bittotime characteristic [22], respectively. Whereas in PLLs this poses a limited issue, since referencepath noise is largely suppressed by their narrow loop bandwidth, MDLLs suffer from a severe degradation in the output spectrum as a result of their much larger injection bandwidth. In fact, since the reference signal is used by MDLLs to provide a baseline for the jitter reset in the RO, DTC jitter is transferred to the output asis. As illustrated by the plot in Fig. 4.3, this additional burden leads to a substantial performance gap between the jitterpowerproduct figureofmerit (FoM) of integerN and fractionalN inductorless frequency synthesizers, which prevents the latter from being adopted in more demanding applications.
3 JitterPower Tradeoff Analysis
To overcome the limitations of the conventional fractionalN MDLL architecture and enable lowjitter and lowpower operation, it is crucial to gain an indepth understanding for its fundamental design tradeoffs. For the case of PLLs, [25] provides appropriate guidelines to minimize the jitterpower product, in terms of an optimum loop bandwidth and power partitioning ratio among building blocks. However, since MDLLs rely mainly on edgereplacement to achieve oscillator phase noise filtering, shifting the loop bandwidth would have little effect on the overall output jitter. Therefore, an analytical expression for the jitterpower product should be first derived for the specific case of MDLL, and then analyzed to determine which degrees of freedom are available for the designer to optimize the overall system performance.
To this end, accurate yet simple expressions for the oscillator and reference path jitter contributions can be derived by leveraging the spectral estimates developed in [26] through a timevariant modeling approach. The following assumptions—which hold in almost all practical cases—will be considered for simplicity: (i) the output jitter is whitenoise limited, i.e. the contribution of 1/f noise to the overall spectrum is negligible, and (ii) the phase noise filtering effect of the tuning loop is negligible compared to that given by the much larger injection bandwidth.
The output jitter contribution due to the RO can be derived by first approximating the MDLL output phase noise spectrum through a Lorentzian function [21]:
where \(K_{inj}\) and \(f_{inj}\) represent the estimates derived in [26] for the lowfrequency plateau and equivalent filtering bandwidth of an edgerealigned RO, given by:
where \(\mathcal {L}_{ro}(f_{ref})\) is the singlesidebandtocarrier ratio of the freerunning oscillator, evaluated at the reference frequency, \(f_{ref}\). The corresponding output phase noise variance, \(\sigma ^2_{\phi ,ro}\), can then be derived by symbolic integration of (4.1). Scaling the result to obtain jitter, leads to:
where the multiplication factor has been assumed to be \(N\gg 1\). To link the jitter contribution to the respective power dissipated in the RO, \(P_{ro}\), the commonly adopted figureofmerit for oscillators, i.e. \(\text {FoM}_{ro} = 10\log _{10} [\mathcal {L}_{ro}(f_{ref}) \cdot (\nicefrac {f_{ref}}{f_{out}})^2 \cdot (\nicefrac {P_{ro}}{\text {1mW}})]\), can be substituted in the previous expression. This ultimately results in:
Since MDLLs rely on the reference edges to provide a baseline to which the RO edges are periodically reset [26], the output jitter contribution due to the reference path is, instead, transferred from the input asis, i.e. \(\sigma ^2_{t,ref} = \sigma ^{2}_{t,in}\). To link also this contribution to the corresponding power consumption, an appropriate figureofmerit can be introduced. Under the assumption that the reference path components (i.e. DTC and buffers) are CMOSbased, their jitter variance can be shown to be proportional to the reference clock frequency and inversely to the dissipated power [23]. This suggests the following figureofmerit:
As a result, the reference path jitter contribution can be expressed as:
To derive an expression for overall jitterpower product figureofmerit (FoM) [25] for MDLLs, (4.4) and (4.6) can be summed and multiplied by the total power consumption, \(P_{ro}+P_{ref}\), leading to:
where the ratio between reference path and RO power has been defined as \(R = P_{ref} / P_{ro}\). Given that the reference and RO contributions in (4.7) exhibit opposite dependencies on N and R, it is reasonable to assume that a global minimum for the jitterpower product may indeed exist. To determine its value, the partial derivatives of (4.7) with respect to N and R are taken and set to zero. The resulting system of two equations in two unknowns can be solved for N and R, leading to the following expressions for their optimum values:
That is, the lowest jitterpower product is obtained when oscillator and reference path power dissipation are balanced, i.e. \(P_{ro} = P_{ref}\), and when an optimum reference frequency (i.e. the multiplication factor, N) is selected. The corresponding expression of the optimum jitterpowerproduct figureofmerit can be found by plugging (4.8) into (4.7), which results in:
Since the optimum FoM value in (4.9) is proportional to the sum of the individual RO and reference FoMs, the system efficiency can in principle be further improved by acting on either of those two quantities. In practice, however, the ringoscillator component is bound by thermodynamic limits to a minimum value of \(165\) dB [28], which can hardly be improved. The reference path, on the other hand, contains a DTC to operate the MDLL in fractionalN mode, which provides additional degrees of freedom to be leveraged. In fact, the analysis presented in [23] suggest two key guidelines to this regard:

CMOS DTCs should be preferred over fullydifferential implementations, since their jitterpower performance is remarkably superior in typical application cases;

For a given DTC architecture, reducing the required delayrange provides the main and most effective way to decrease jitter and thus improve \(\text {FoM}_{ref}\).
In addition to the jitterpower product, several other DTC designtradeoffs benefit from a reduction of its range as well. DTC nonlinearity, for example, also depends on the delayrange [29]. Reducing it has therefore a positive impact on linearity and, in turn, on calibration complexity and fractionalspur performance. Furthermore, since the individual delaycells typically dominate the area required for a given DTC design, reducing the range is also beneficial to the area occupation.
4 DTC RangeReduction Technique
As outlined in the previous section, reducing DTC range entails several advantages for fractionalN MDLL design. Nevertheless, given that proper edgesynchronization has to be preserved in order not to degrade the output spectrum, achieving any significant rangereduction represents a nontrivial task. To overcome these limitations, Fig. 4.4 introduces a technique that—by acting on both the injection path as well as the tuning loop—allows to achieve a substantial reduction in DTC range, without incurring in any edgemisalignment issues [10].
In regard to the injection path, range reduction is achieved as follows. Assuming that the oscillator dutycycle is 50%,^{Footnote 1} an opposite polarity edge is available every \(T_v/2\). In principle, since only an alignment to the nearest edge is necessary for the injection to be performed correctly, the DTC range can be reduced to \(T_v/2\). If a specific RO edge then happens to be of opposite polarity with respect to the reference one, correct realignment can still be recovered by leveraging a differential oscillator implementation, and simply swapping the injected signal around. The corresponding signal diagrams, for the simpler case of a firstorder \(\Delta \Sigma \)modulator, are shown in Fig. 4.4b. Conventionally, the delay required from the DTC follows a ramp from 0 to \(T_v\), as a result of the quantization noise amplitude introduced by the \(\Delta \Sigma \)modulator. By resetting the DTC control word in the second part of the delayramp, i.e. after a maximum \(T_v/2\) delay has been reached, the rising reference edges become aligned with falling edges in the oscillator. To match edge polarity, the reference signal is then swapped around according to the value of a control signal, s[k], which is set to 1 during the second part of the ramp.
The s[k] control signal is derived via a successive requantization of the frequencycontrol word (FCW), as shown in Fig. 4.4a. A multiplication by two (i.e. a shift left) is first performed on the input FCW, so that all bits of the fractional part—except for the MSB—are requantized by the first \(\Delta \Sigma \)modulator. Its output is then divided by two (i.e. shifted right) to restore the correct fractional information. The resulting signal is then fed to a modulo2 accumulator—which essentially behaves like a singlebit firstorder \(\Delta \Sigma \)modulator—to complete the requantization of the fractional part, providing a dithered control signal for the integer divider placed in the frequency acquisition loop. The accumulated quantization error from the first \(\Delta \Sigma \) is used as new control signal for the DTC, whereas the sum output of the modulo2 accumulator finally represents the inversioncontrol signal, s[k].
In the tuning loop, the DTCreset method described so far would lead to a squarewavelike time error at the TDC input, with a corresponding amplitude of \(T_v/2\), which is caused by the missing delay introduced via the DTC. To maintain lock even under these conditions, a powerhungry multibit TDC would generally be required to track the error. Then, to avoid spurious modulations of the RO, this error would additionally require proper canceling at the TDC output. To overcome these issues and allow for lowpower and lowjitter operation, a 1bit TDC operated in subsampling mode is leveraged as follows. Conventionally, 1bit TDCs are used to detect timeerrors in a narrow range around \(\Delta t = 0\), for which they exhibit an equivalent linear gain, \(K_{pd}\) [24]. However, by connecting the TDC in subsampling mode—i.e. by allowing it to directly the oscillator signal instead of the divider output—the time error can be detected with respect to all oscillator edges, virtually increasing its range well above \(\Delta t = 0\). In fact, as illustrated by the lower part of Fig. 4.4b, this results in a 1bit TDC characteristic with a period of \(T_v\) and gain of oppositesign every \(T_v/2\). Therefore, the deterministic squarewavelike time error just shifts the operating point for noise detection in 1bit TDC, either around the \(\Delta t = 0\) region or the \(\Delta t = T_v/2\) one. Since both are able to provide an average linear gain, phase detection is not compromised. To recover the correct timeerror sign, the 1bit TDC output signal, e[k], is then simply inverted according to the value of s[k].
5 Implemented Architecture
Figure 4.5 shows the block diagram of the proposed fractionalN MDLL architecture, which has been implemented in a standard 65 nm CMOS process [10]. The system leverages the proposed DTC rangereduction technique and the results from the jitterpower tradeoff analysis, to achieve both lowjitter and lowpower fine fractionalN frequency synthesis.
The MDLL is based around a fivestage pseudodifferential ring oscillator, which is tuned via currentstarved NMOS transistors [8]. A simple pulser circuit, based on an ANDgate edge detector, identifies the rising edges of the DTCdelayed reference signal to be injected, ref\(_\text {dtc}\), and controls the multiplexer accordingly. A swappingMUX—i.e. a transmissiongatebased multiplexer with an embedded polarity reverser—is used to selectively swap the polarity of the differential injection signal, whenever \(s[k] = 1\). Since static timing offsets between the injection and tuning paths would lead to reference spurs in the MDLL output spectrum, an automatic time offset compensation is additionally used [8].
Fine frequency tuning is achieved via the previously introduced 1bit TDC subsampling loop. Coarse frequency acquisition is instead achieved by means of a digital frequencylocked loop (FLL), based on a variant of [27]. It relies on a lowpower, fivelevel TDC to sense the coarse timing difference between rising edges of the DTCdelayed reference signal, ref\(_\text {dtc}\), and divider output, div. The TDC output is then fed to a digital loop filter, which provides the coarse tuning information for the RO. Once locking has been achieved, the midthread characteristic of the fivelevel TDC ensures that the FLL enters an automatic deadzone state (with negligible power consumption), which is only left if a significant phase disturbance is sensed between ref\(_\text {dtc}\) and div. Since the DTC rangereduction technique determines a residual \(T_v/2\) time error between ref\(_\text {dtc}\) and div, false triggering of the 5level TDC may become an issue in fractionalN mode. To avoid this, the s[k] control signal is also used in the FLL to selectively resample the output of the integerN divider, with either the rising or the falling edge of the oscillator (out). This effectively introduces a \(T_v/2\) additional delay on the divided signal, which compensates for the reduced DTC range on the reference path.
The DTC is segmented into a coarse and a fineresolution stage, both of which are based on a CMOSimplementation in order to improve the overall efficiency. The coarse DTC is implemented as a cascade of buffer cells, with an embedded multiplexer that allows to set the effective length of the delay line. The fine DTC is instead implemented by digitally varying the capacitive load of a CMOS inverter, and thus its delay. Two crosslatched inverters are then additionally used to generate the required pseudodifferential DTC output. The bittotime conversion gain of the two DTCs is adjusted in background by a digital calibration block, which also compensates for their nonlinearity and mismatches.
Since ringoscillators are subject to process, voltage and temperature (PVT) variations that cause their dutycycle to vary, rising and falling edges which will not be exactly \(T_v/2\) apart. This, in turn, would lead to a misalignment between reference signal and the recirculating edges, every time a polarity reversal is performed by the swappingMUX. To avoid the resulting degradation in the output spectrum, a leastmeansquare (LMS) based dutycycle corrector (DCC) has also been implemented. The DCC operates in background and provides an output value which, summed to the DTC control word, allows to cancel the timing mismatches between reference and RO edges through the DTC itself.
To minimize the overall jitterpower product, the MDLL multiplication factor has been chosen according to (4.8), and the power budget for the RO and referencepath components has been equalized as closely as possible. Overall, the blocks running at the reference frequency dissipate 1.64 mW at 100 MHz, and introduce about 300 fs RMS jitter, leading to \(\text {FoM}_{ref} = 328\) dB. The RO, instead, dissipates \(860 \ \upmu \)W and exhibits \(119\) dBc/Hz phase noise at an offset of 10 MHz, leading to \(\text {FoM}_{ro} = 164\) dB. As a result, the optimum value for the multiplication factor is \(N_{opt} = 16\), with a corresponding expected theoretical \(\text {FoM}_{opt} =242\) dB.^{Footnote 2}
6 Measurement Results
The prototype, whose die micrograph is shown in Fig. 4.6, has been implemented in a standard 65 nm CMOS process. It occupies a total core area of 0.0275 mm\(^2\), with 0.0175 mm\(^2\) reserved for the digital core and 0.01 mm\(^2\) for the analog blocks (excluding the output buffer). The system is capable of fine fractionalN frequency synthesis in the 1.6to3.0 GHz range, with a resolution of around 190 Hz. At 1.6 GHz, the synthesizer core dissipates 2.5 mW from a 1.2 V supply.
Figure 4.7 provides the phase noise measurement in both the integerN and fractionalN modes, as well as the freerunning ringoscillator profile, around 1.6 GHz. The corresponding RMS jitter values (integrated from 30 kHz to 30 MHz) are 334 fs and 397 fs, for the integerN and the fractionalN case, respectively. At 1 MHz offset from the carrier, the phase noise level is \(122.37\) dBc/Hz in the fractionalN mode.
Table 4.1 provides a summary of the measured performances, as well as a comparison to other stateoftheart fractionalN inductorless frequency synthesizers. In the fractionalN mode, the synthesizer reaches a jitterpower FoM of \(244\) dB, achieving an almost 10 dB improvement over previous stateoftheart, and effectively bridging the gap to integerN implementations (see previous Fig. 4.3). The corresponding bandwidthnormalized FoM\(_\text {norm}\), which accounts for the limited jitter integration bandwidth in measurements [10], is \(240\) dB. The 2 dB discrepancy with respect to the theoretical \(242\) dB prediction derived in Sect. 4.5, is likely due to a residual power imbalance between oscillator and reference path, as well as to the Lorentzian approximation used for the spectra.
7 Conclusion
The increasing demand for lowcost wireless solutions, drives the pursuit of frequency synthesizers with very small overall area occupation. In this chapter, the design of a highly compact yet efficient inductorless frequency synthesizer has been presented. Based on a multiplying delaylocked loop architecture, the system achieves both lowjitter and lowpower fractionalN operation, by leveraging the results from a systemlevel jitterpower tradeoff analysis, combined with the introduction of a novel DTC rangereduction technique. The synthesizer, implemented in a standard 65 nm CMOS process, achieves a record jitterpower FoM of \(244\) dB in the fractionalN mode, in a compact 0.0275 mm\(^2\) core area.
Notes
 1.
This assumption will be relaxed in the next section, where an automatic correction circuit is introduced to account for non50% dutycycles.
 2.
This estimate assumes an infinite jitter integration bandwidth. To account for the limited integration bandwidth in measurements, a correction factor of \((2/\pi ) \cdot \log _{10}[\tan ^{1}(\nicefrac {f_\text {meas}}{f_\text {inj})}]\) can be introduced, where \(f_\text {meas}\) is the upper measurement limit and \(f_\text {inj}\) is the injection bandwidth [10].
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Acknowledgements
This work has been supported by Intel Corporation. The author wishes to thank Dr. Mario Mercandelli, Prof. Salvatore Levantino, Prof. Carlo Samori and Prof. Andrea L. Lacaita for the useful discussions.
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Santiccioli, A. (2021). Inductorless Frequency Synthesizers for LowCost Wireless. In: Geraci, A. (eds) Special Topics in Information Technology. SpringerBriefs in Applied Sciences and Technology(). Springer, Cham. https://doi.org/10.1007/9783030624767_4
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