Advertisement

Succinct Monotone Circuit Certification: Planarity and Parameterized Complexity

Conference paper
  • 293 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 12273)

Abstract

Monotone Boolean circuits are circuits where each gate is either an \(\texttt {AND}\) gate or an \(\texttt {OR}\) gate. In other words, negation gates are not allowed in monotone circuits. This class of circuits has sparked the attention of researchers working in several subfields of combinatorics and complexity theory. In this work, we introduce the notion of certification-width of a monotone Boolean circuit, a complexity measure that intuitively quantifies the minimum number of edges that need to be traversed by a minimal set of positive weight inputs in order to certify that C is satisfied. We call the problem of computing this new invariant, the Succinct Monotone Circuit Certification (SMCC) problem. We prove that SMCC is NP-complete even when the input monotone circuit is planar. Subsequently, we show that the problem is W[1]-hard, but still in W[P], when parameterized by the size of the solution. We also show that SMCC is fixed-parameter tractable when restricted to monotone circuits of bounded genus. In contrast, we show that SMCC on planar circuits does not admit a polynomial kernel, unless NP \(\subseteq \) coNP/poly.

Keywords

Monotone circuits Planarity Genus FPT Treewidth 

References

  1. 1.
    Barrington, D.A.M., Lu, C.-J., Miltersen, P.B., Skyum, S.: On monotone planar circuits. In: Proceedings of the Fourteenth Annual IEEE Conference on Computational Complexity, pp. 24–31 (1999)Google Scholar
  2. 2.
    Cai, L., Fellows, M., Juedes, D., Rosamond, F.: The complexity of polynomial-time approximation. Theory Comput. Syst. 41(3), 459–477 (2007)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Creignou, N., Vollmer, H.: Parameterized complexity of weighted satisfiability problems: decision, enumeration, counting. Fundam. Inform. 136(4), 297–316 (2015)MathSciNetCrossRefGoogle Scholar
  4. 4.
    Cygan, M., et al.: Lower bounds for kernelization. In: Parameterized Algorithms, pp. 523–555. Springer, Cham (2015).  https://doi.org/10.1007/978-3-319-21275-3_15
  5. 5.
    Downey, R.G., Fellows, M.R.: Parameterized Complexity. Springer, New York (2012)zbMATHGoogle Scholar
  6. 6.
    Fellows, M.R., Hermelin, D., Rosamond, F.A., Vialette, S.: On the parameterized complexity of multiple-interval graph problems. Theoret. Comput. Sci. 410(1), 53–61 (2009)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Fomin, F.V., Golovach, P., Thilikos, D.M.: Contraction obstructions for treewidth. J. Comb. Theor. Ser. B 101(5), 302–314 (2011)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Gross, J.L., Tucker, T.W.: Topological Graph Theory. Courier Corporation (2001)Google Scholar
  9. 9.
    Gu, Q.P., Tamaki, H.: Improved bounds on the planar branchwidth with respect to the largest grid minor size. Algorithmica 64(3), 416–453 (2012)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Kanj, I., Thilikos, D.M., Xia, G.: On the parameterized complexity of monotone and antimonotone weighted circuit satisfiability. Inf. Comput. 257, 139–156 (2017)MathSciNetCrossRefGoogle Scholar
  11. 11.
    Khanna, S., Motwani, R.: Towards a syntactic characterization of PTAS. In: Proceedings of the Twenty-Eighth Annual ACM Symposium on Theory of Computing, pp. 329–337 (1996)Google Scholar
  12. 12.
    Limaye, N., Mahajan, M., Sarma, J.M.: Upper bounds for monotone planar circuit value and variants. Comput. Complex. 18(3), 377 (2009)MathSciNetCrossRefGoogle Scholar
  13. 13.
    Marx, D.: Completely inapproximable monotone and antimonotone parameterized problems. J. Comput. Syst. Sci. 79(1), 144–151 (2013)MathSciNetCrossRefGoogle Scholar
  14. 14.
    Nilsson, N.J.: Problem-solving methods in artificial intelligence. McGraw-Hill Computer Science Series. McGraw-Hill, New York (1971)Google Scholar
  15. 15.
    Robertson, N., Seymour, P., Thomas, R.: Quickly excluding a planar graph. J. Comb. Theor. Ser. B 62(2), 323–348 (1994)MathSciNetCrossRefGoogle Scholar
  16. 16.
    Robertson, N., Seymour, P.D.: Graph minors. J. Comb. Theor. Seri. B 36(1), 49–64 (1984)Google Scholar
  17. 17.
    Savage, J.E.: Planar circuit complexity and the performance of VLSI algorithms+. In: VLSI Systems and Computations, pp. 61–68. Springer, Heidelberg (1981)Google Scholar
  18. 18.
    Souza, U.S., Protti, F.: Tractability, hardness, and kernelization lower bound for and/or graph solution. Discrete Appl. Math. 232, 125–133 (2017)MathSciNetCrossRefGoogle Scholar
  19. 19.
    Souza, U.S., Protti, F., da Silva, M.D.: Revisiting the complexity of and/or graph solution. J. Comput. Syst. Sci. 79(7), 1156–1163 (2013)MathSciNetCrossRefGoogle Scholar
  20. 20.
    Szeider, S.: On fixed-parameter tractable parameterizations of SAT. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol. 2919, pp. 188–202. Springer, Heidelberg (2004).  https://doi.org/10.1007/978-3-540-24605-3_15CrossRefzbMATHGoogle Scholar
  21. 21.
    Turán, G.: On the complexity of planar boolean circuits. Comput. Complex. 5(1), 24–42 (1995)MathSciNetCrossRefGoogle Scholar
  22. 22.
    Uchizawa, K., Douglas, R., Maass, W.: On the computational power of threshold circuits with sparse activity. Neural Comput. 18(12), 2994–3008 (2006)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Instituto de ComputaçãoUniversidade Federal FluminenseNiteróiBrazil
  2. 2.Department of InformaticsUniversity of BergenBergenNorway
  3. 3.Instituto Federal do Tocantins, Campus Porto NacionalPorto NacionalBrazil

Personalised recommendations