Abstract
FALCON is a lattice-based cryptographic algorithm which claims to provide a signature scheme that is unforgeable against quantum-computers; it is the second such algorithm we consider in-depth, of the eight in this book. This algorithm is divided into three components: key generation, signature generation, and signature verification. We select three variants of FALCON with distinct security strength and make these variants capable of synthesis by a High-Level Synthesis (HLS) tool. We summarize all the changes in the C code to make it capable of synthesis. Using HLS, we generate FPGA and ASIC designs for signature verification of three variants. For FALCON hardware architectures, we evaluate trade-offs in power, area, speed, and security parameters. We explore the design-space through a detailed analysis of FPGA and ASIC designs for FALCON, concluding that for the FPGA implementation, latency increases with security while for the ASIC-specific implementation, loop pipelining improves the latency without any additional memory or area cost.
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Soni, D., Basu, K., Nabeel, M., Aaraj, N., Manzano, M., Karri, R. (2021). FALCON. In: Hardware Architectures for Post-Quantum Digital Signature Schemes. Springer, Cham. https://doi.org/10.1007/978-3-030-57682-0_3
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DOI: https://doi.org/10.1007/978-3-030-57682-0_3
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