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Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 12083)


Field-programmable gate array (FPGA) based accelerators are being widely used for acceleration of convolutional neural networks (CNNs) due to their potential in improving the performance and reconfigurability for specific application instances. To determine the optimal configuration of an FPGA-based accelerator, it is necessary to explore the design space and an accurate performance prediction plays an important role during the exploration. This work introduces a novel method for fast and accurate estimation of latency based on a Gaussian process parametrised by an analytic approximation and coupled with runtime data. The experiments conducted on three different CNNs on an FPGA-based accelerator on Intel Arria 10 GX 1150 demonstrated a 30.7% improvement in accuracy with respect to the mean absolute error in comparison to a standard analytic method in leave-one-out cross-validation.


  • Field-programmable gate array
  • Deep learning
  • Convolutional neural network
  • Performance estimation
  • Gaussian process

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  1. 1.

    A tutorial code is available at

  2. 2.

    For a detailed derivation please refer to [15].


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We thank Yann Herklotz, Alexander Montgomerie-Corcoran and ARC’20 reviewers for insightful suggestions.

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Correspondence to Martin Ferianc .

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Ferianc, M., Fan, H., Chu, R.S.W., Stano, J., Luk, W. (2020). Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks. In: Rincón, F., Barba, J., So, H., Diniz, P., Caba, J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science(), vol 12083. Springer, Cham.

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