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High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 12083)

Abstract

Compared to traditional hardware development methodologies, High-Level Synthesis (HLS) offers a faster time-to-market and lower design cost at the expense of implementation efficiency. Although Software/Hardware Codesign has been used in many areas, its usability for benchmarking of candidates in cryptographic competitions has been largely unexplored. This paper provides a comparison of the HLS- and RTL-based design methodologies when applied to the hardware design of the Number Theoretic Transform (NTT) – a core arithmetic function of lattice-based Post-Quantum Cryptography (PQC). As a next step, we apply Software/Hardware Codesign approach to the implementation of three PQC schemes based on NTT. Then, we integrate our HLS implementation into the Xilinx SDSoC environment. We demonstrate that an overhead of SDSoC compared to traditional Bare Metal approach is acceptable. This paper also shows that an HLS implementation obtained by modeling a block diagram is typically much better than an implementation obtained by using design space exploration. We conclude that the HLS/SDSoC and RTL/Bare Metal approaches generate comparable results.

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  • DOI: 10.1007/978-3-030-44534-8_19
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References

  1. NIST Post-Quantum Cryptography Standardization

    Google Scholar 

  2. Farahmand, F., Dang, V.B., Nguyen, D.T., Gaj, K.: Evaluating the potential for hardware acceleration of four NTRU-based key encapsulation mechanisms using software/hardware codesign. In: Ding, J., Steinwandt, R. (eds.) PQCrypto 2019. LNCS, vol. 11505, pp. 23–43. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-25510-7_2

    CrossRef  Google Scholar 

  3. Chu, E., George, A.: Inside the FFT Black Box: Serial and Parallel Fast Fourier Transform Algorithms. Computational Mathematics Series. CRC Press, Boca Raton (2019)

    Google Scholar 

  4. Longa, P., Naehrig, M.: Speeding up the number theoretic transform for faster ideal lattice-based cryptography. In: Foresti, S., Persiano, G. (eds.) CANS 2016. LNCS, vol. 10052, pp. 124–139. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-48965-0_8

    CrossRef  Google Scholar 

  5. Pöppelmann, T., Güneysu, T.: Towards efficient arithmetic for lattice-based cryptography on reconfigurable hardware. In: Hevia, A., Neven, G. (eds.) LATINCRYPT 2012. LNCS, vol. 7533, pp. 139–158. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-33481-8_8

    CrossRef  Google Scholar 

  6. Du, C., Bai, G., Wu, X.: High-speed polynomial multiplier architecture for ring-LWE based public key cryptosystems. In: GLSVLSI (2016)

    Google Scholar 

  7. Renteria-Mejia, C.P., Velasco-Medina, J.: High-throughput ring-LWE cryptoprocessors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(8), 2332–2345 (2017)

    CrossRef  Google Scholar 

  8. Oder, T., Güneysu, T.: Implementing the NewHope-Simple key exchange on low-cost FPGAs. In: Lange, T., Dunkelman, O. (eds.) LATINCRYPT 2017. LNCS, vol. 11368, pp. 128–142. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-25283-0_7

    CrossRef  Google Scholar 

  9. Kuo, P.-C., et al.: High performance post-quantum key exchange on FPGAs. Cryptology ePrint Archive 2017/690, February 2018

    Google Scholar 

  10. Homsirikamol, E., Gaj, K.: Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: the SHA-3 contest case study. In: Sano, K., Soudris, D., Hübner, M., Diniz, P.C. (eds.) ARC 2015. LNCS, vol. 9040, pp. 217–228. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-16214-0_18

    CrossRef  Google Scholar 

  11. Homsirikamol, E., Gaj, K.: A new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: the CAESAR contest case study. In: FPT 2017 (2017)

    Google Scholar 

  12. Kawamura, K., Yanagisawa, M., Togawa, N.: A loop structure optimization targeting high-level synthesis of fast number theoretic transform. In: ISQED (2018)

    Google Scholar 

  13. Knuth, D.E.: The Art of Computer Programming, Fundamental Algorithms. Addison-Wesley, Boston (1997)

    MATH  Google Scholar 

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Correspondence to Kris Gaj .

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Nguyen, D.T., Dang, V.B., Gaj, K. (2020). High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign. In: Rincón, F., Barba, J., So, H., Diniz, P., Caba, J. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science(), vol 12083. Springer, Cham. https://doi.org/10.1007/978-3-030-44534-8_19

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  • DOI: https://doi.org/10.1007/978-3-030-44534-8_19

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