Abstract
In this work, we present an optimized pipelined hardware implementation of the accelerated Simple Linear Iterative Clustering algorithm (A-SLIC) for superpixel segmentation. The algorithm is implemented on an FPGA using a hardware-software co-design framework wherein large memory requirements are drawn from off-chip memory. On-Chip resource and time optimization are achieved by employing fixed-point computations and the table look-up for computing color space conversion in place of floating point operations. Also, the color conversion and the distance calculation loops are pipelined for the increased throughput. The design is implemented on the Zynq-7000 system-on-chip (SOC). The component usage, memory requirements, and the segmentation quality using standardized metrics are evaluated and presented for benchmark images. Compared to the sequential software implementation of the SLIC on a CPU, the proposed algorithm executed on the Zynq 7000 device achieves speed up of 10–22.
Keywords
- Superpixel
- Algorithm acceleration
- Co-design
- High-level synthesis (HLS)
- Zynq 7000 SOC
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Ghimire, M., Regentova, E., Muthukumar, V. (2020). A -SLIC: Acceleration of SLIC Superpixel Segmentation Algorithm in a Co-Design Framework. In: Latifi, S. (eds) 17th International Conference on Information Technology–New Generations (ITNG 2020). Advances in Intelligent Systems and Computing, vol 1134. Springer, Cham. https://doi.org/10.1007/978-3-030-43020-7_90
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DOI: https://doi.org/10.1007/978-3-030-43020-7_90
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