Abstract
Timing analysis of safety-critical systems derives timing bounds of applications, or software (SW), executed on dedicated platforms, or hardware (HW). The ensemble HW–SW features, from a timing perspective, two different types of computation – a SW-specific, instruction-driven timing progression and a HW-specific, cycle-driven one. The two timings are unified under a concept of timing model, which is crucial to establish a sound and precise worst-case timing reasoning. In this paper, we propose an investigation on how to systematically derive and formally prove such timing models. Our approach is exemplified on a simple, accumulator-based processor called Lipsi.
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Asavoae, M., Haur, I., Jan, M., Ben Hedia, B., Schoeberl, M. (2020). Towards Formal Co-validation of Hardware and Software Timing Models of CPSs. In: Chamberlain, R., Edin Grimheden, M., Taha, W. (eds) Cyber Physical Systems. Model-Based Design. CyPhy WESE 2019 2019. Lecture Notes in Computer Science(), vol 11971. Springer, Cham. https://doi.org/10.1007/978-3-030-41131-2_10
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