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XMSS and Embedded Systems

XMSS Hardware Accelerators for RISC-V
  • Wen WangEmail author
  • Bernhard Jungk
  • Julian Wälde
  • Shuwen Deng
  • Naina Gupta
  • Jakub SzeferEmail author
  • Ruben NiederhagenEmail author
Conference paper
  • 109 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11959)

Abstract

We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By integrating our hardware accelerators into the RISC-V processor, the version with the best time-area product generates a key pair (that can be used to generate \(2^{10}\) signatures) in 3.44 s, achieving an over \(54 \times \) speedup in wall-clock time compared to the pure software version. For such a key pair, signature generation takes less than 10 ms and verification takes less than 6 ms, bringing speedups of over \(42 \times \) and \(17 \times \) respectively. We tested and measured the cycle count of our implementation on an Intel Cyclone V SoC FPGA. The integration of our XMSS accelerators into an embedded RISC-V processor shows that it is possible to use hash-based post-quantum signatures for a large variety of embedded applications.

Keywords

XMSS Hash-based signatures Post-quantum cryptography Hardware accelerator FPGA RISC-V 

Notes

Acknowledgments

This work was supported in part by NSF grant 1716541. Part of the research was performed when the second author was affiliated with Fraunhofer Singapore.

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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Yale UniversityNew HavenUSA
  2. 2.MunichGermany
  3. 3.Fraunhofer SITDarmstadtGermany
  4. 4.Fraunhofer SingaporeSingaporeSingapore

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