Advertisement

Parallelware Tools: An Experimental Evaluation on POWER Systems

  • Manuel ArenazEmail author
  • Xavier Martorell
Conference paper
  • 4.9k Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11887)

Abstract

Static code analysis tools are designed to aid software developers to build better quality software in less time, by detecting defects early in the software development life cycle. Even the most experienced developer regularly introduces coding defects. Identifying, mitigating and resolving defects is an essential part of the software development process, but frequently defects can go undetected. One defect can lead to a minor malfunction or cause serious security and safety issues. This is magnified in the development of the complex parallel software required to exploit modern heterogeneous multicore hardware. Thus, there is an urgent need for new static code analysis tools to help in building better concurrent and parallel software. The paper reports preliminary results about the use of Appentra’s Parallelware technology to address this problem from the following three perspectives: finding concurrency issues in the code, discovering new opportunities for parallelization in the code, and generating parallel-equivalent codes that enable tasks to run faster. The paper also presents experimental results using well-known scientific codes and POWER systems.

Keywords

Static code analysis Quality assurance and testing Detection of software defects Concurrency and parallelism Parallelware tools OpenMP Tasking POWER systems 

Notes

Acknowledgements

This work has been partly funded from the Spanish Ministry of Science and Technology (TIN2015-65316-P), the Departament d’Innovació, Universitats i Empresa de la Generalitat de Catalunya (MPEXPAR: Models de Programació i Entorns d’Execució Parallels, 2014-SGR-1051), and the European Union’s Horizon 2020 research and innovation program through grant agreements MAESTRO (801101) and EPEEC (801051). The authors gratefully acknowledge the access to the Juron system at Jülich Supercomputing Centre.

References

  1. 1.
    Andión, J., Arenaz, M., Rodríguez, G., Touriño, J.: A novel compiler support for automatic parallelization on multicore systems. Parallel Comput. 39(9), 442–460 (2013)CrossRefGoogle Scholar
  2. 2.
    Appentra. Defects and Recommendations for Concurrency and Parallelism (2019). https://www.appentra.com/knowledge
  3. 3.
    Appentra. Parallelware tools (2019). http://www.appentra.com
  4. 4.
    Arenaz, M., Touriño, J., Doallo, R.: XARK: an extensible framework for automatic recognition of computational kernels. ACM Trans. Program. Lang. Syst. (TOPLAS) 30(6), 32:1–32:56 (2008)CrossRefGoogle Scholar
  5. 5.
    Bailey, D., et al.: The NAS parallel benchmarks - summary and preliminary results. In: Proceedings of the 1991 ACM/IEEE Conference on Supercomputing, Supercomputing 1991, pp. 158–165. ACM (1991)Google Scholar
  6. 6.
    Center for Manycore Programming, Seoul National University (SNU). SNU NPB Suite (2013). http://aces.snu.ac.kr/software/snu-npb/
  7. 7.
    OpenACC Architecture Review Board. The OpenACC Application Programming Interface, Version 2.5, October 2015. http://www.openacc.org
  8. 8.
    OpenMP Architecture Review Board. OpenMP Application Program Interface, Version 4.5, November 2015. http://www.openmp.org

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.University of A CorunaA CoruñaSpain
  2. 2.Appentra SolutionsA CoruñaSpain
  3. 3.Computer Architecture DepartmentUniversitat Politécnica de CatalunyaBarcelonaSpain
  4. 4.Computer Sciences DepartmentBarcelona Supercomputing CenterBarcelonaSpain

Personalised recommendations