New Residue Signed-Digit Addition Algorithm

Abstract

In this paper, we propose a new residue signed-digit (SD) addition algorithm, which can be used in RSA public-key cryptosystem with a large modulus m. We use $\upmu = {\text{m}} - 2^{n}$ and $- 2^{n - 1} + 1\, \le \,\mu \, < \,0$ to calculate the residue n-digit SD number additions. Thus, the residue addition is implemented by (1) adding two n-digit SD numbers and (2) reducing the (n+1)-digit SD number obtained by the SD addition to an n-digit SD number using $\mu$. Thus, the circuit of residue SD adder is constructed with two SD adders and some multiplexers, and no carry propagations arise during the residue addition. We have designed the circuits with VHDL for the encryption processor using the proposed residue SD adders. By comparing the performance of the encryption processor with that of the binary architectures, the proposed encryption processor is superior to the binary ones in computing time and low power.