Abstract
Full adder being the basic building block that performs many operations like addition, division, multiplication and other similar arithmetic process in VLSI systems. Dayadi 1-bit CMOS FA implemented by using CMOS circuits and transmission gate circuits is presented. Design of Dayadi 1-bit CMOS full adder Based on Power Reduction Techniques. The sum and carry generation circuits are designed by novel logic style. The circuit was implemented using micro wind tools in cmos-90 nm technology. Factors such as no of transistors, propagation delay, PDP, and chip area were compared with the existing designs such full adder, TGL and so on. The ultimate aim of designing Dayadi 1-bit CMOS full adder is to reduce power dissipation and to decreased the delay compared to existing work performance.
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Bhattacharyya P, Ghosh S, Kumar V (2015) Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(10):2001–2008
Megha V (2017) Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit using CMOS technologies using Cadance. Int Res J Eng Technol (IRJET) 04(08):1931–1938 e-ISSN 2395-0056
Tung C-K, Hung Y-C, Shieh S-H, Huang G-S (2014) A low-power high-speed hybrid CMOS full adder for embedded system. In: Proceedings of IEEE conference on design diagnostics electronic circuits and systems, vol 13, April 2014, pp 1–4
Goel S, Kumar A, Bayoumi MA (2013) Design of robust, energy efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(12):1309–1321
Weste NHE, Harris D, Banerjee A (2012) CMOS VLSI design: a circuits and systems perspective, 3rd edn. Pearson Education, Delhi
Rabaey JM, Chandrakasan A, Nikolic B (2012) Digital integrated circuits: a design perspective, 2nd edn. Pearson Education, Delhi
Radhakrishnan D (2001) Low-voltage low-power CMOS full adder. IEE Proc-Circ Devices Syst 148(1):19–24
Zimmermann R, Fichtner W (1997) Low-power logic styles: CMOS versus pass-transistor logic. IEEE J Solid-State Circ 32(7):1079–1090
Chang CH, Gu JM, Zhang M (2005) A review of 0.18-μm full adder performances for tree structured arithmetic circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(6):686–695
Aranda ML, Báez R, Diaz OG (2010) Hybrid adders for high-speed arithmetic circuits: a comparison. In: Proceedings of 7th IEEE International Conference on Electrical Engineering Computing Science and Automatic Control (CCE), Tuxtla Gutierrez, NM, USA, September 2010, pp 546–549
Vesterbacka M (2003) A 14-transistor CMOS full adder with full voltage swing nodes. In: Proceedings of IEEE Workshop Signal Processing Systems (SiPS), Taipei, Taiwan, October 1999, pp 713–722
Zhang M, Gu J, Chang C-H (2003) A novel hybrid pass logic with static CMOS output drive full-adder cell. In: Proceedings of International Symposium on Circuits and Systems, May 2003, pp 317–320
Acknowledgment
The author here by acknowledgment their deep gratitude to the management of VBIT institute of technology, Hyderabad to have proved the laboratory facilities for developing this project and also special thanks to Dr. Dayadi Lakshmaiah and Mrs. Manga J. for the proper guidance and special thanks to, our Vignana Bharathi Institute of Technology, Hyderabad, India chairmen Goutham Rao sir, secretary Manohar Reddy sir principal, Jayanth Kulakarni sir, ECE HOD Dr. Y. Srineevas sir and R&D Department.
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Sowmya, P., Lakshmaiah, D., Manga, J., Sai Shankar, G., Sai Prasad, D. (2020). Design of Dayadi 1-bit CMOS Full Adder Based on Power Reduction Techniques. In: Satapathy, S.C., Raju, K.S., Shyamala, K., Krishna, D.R., Favorskaya, M.N. (eds) Advances in Decision Sciences, Image Processing, Security and Computer Vision. ICETE 2019. Learning and Analytics in Intelligent Systems, vol 4. Springer, Cham. https://doi.org/10.1007/978-3-030-24318-0_11
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DOI: https://doi.org/10.1007/978-3-030-24318-0_11
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