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Filter Algorithms

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Digital Filters Using MATLAB

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Abstract

In this chapter, we discuss basic properties of digital algorithms, i.e., computations order of difference equations, precedence graphs, latency, throughput, sequentially computable algorithms. In addition we discuss methods to derive the precedence form from the signal-flow graph, and computation graphs. We discuss the concept of maximal sample frequency and how it can be obtained, i.e., cyclic scheduling, pipelining and interleaving. We also discuss fixed-point arithmetic, realisation of multiplication and its simplification, multiple-constant multiplication and sum-of-products. Finally, we discuss power consumption and voltage scaling in CMOS circuits. The chapter contains 8 solved examples.

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Notes

  1. 1.

    The word “algorithm” is derived from the name of the ninth-century Persian mathematician, Abu Ja´far Muhammad ibn Musa al-Khuwarizmi, 780–850.

References

  1. Crochiere, R.E., Oppenheim, A.V.: Analysis of linear digital networks. IEEE Proc. 63(4), 581–595 (1975)

    Article  Google Scholar 

  2. Wanhammar L.: DSP Integrated Circuits. Academic Press (1999)

    Google Scholar 

  3. Fettweis, A.: Realizability of digital filter networks. Archiv fur Elektronik und Übertragungstechnik 30(2), 90–96 (1976)

    Google Scholar 

  4. Renfors, M., Neuvo, Y.: The maximal sampling rate of digital filters under hardware speed constraints. IEEE Trans. Circuits Syst. 28(3), 196–202 (1981)

    Article  Google Scholar 

  5. Chandrakasan A.P., Potkonjak, M., Mehra, R., Rabay, J., Brodersen, R.W.: Optimizing power using transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), 12–31 (1995)

    Article  Google Scholar 

  6. Claesen, L., De Man, H.J., Vandewalle, J.: Delay management algorithms for digital filter implementations. In: Sixth European Conference on Circuit Theory and Design, ECCTD-83, pp. 479–482, Stuttgart, Germany, Sept 1983

    Google Scholar 

  7. Lee, E.A., Messerschmitt, D.G.: Pipeline interleaved programmable DSP’s: architecture. IEEE Trans. Acoust. Speech Signal Process. 35(9), 1320–1333 (1987)

    Article  Google Scholar 

  8. Lee, E.A., Messerschmitt, D.G.: Synchronous data flow. IEEE Proc. 75(9), 1235–1245 (1987)

    Article  Google Scholar 

  9. Parhi, K.K., Messerschmitt, D.G.: Pipeline interleaving and parallelism in recursive digital filters—part I: pipelining using scatter look-ahead and decomposition. IEEE Trans. Acoust. Speech Signal Process. 37(7), 1099–1117 (1989)

    Google Scholar 

  10. Parhi, K.K., Messerschmitt, D.G.: Pipeline interleaving and parallelism in recursive digital filters—part II: pipelining incremental block filtering. IEEE Trans. Acoust. Speech, Signal Process. 37(7), 1118–1134 (1989)

    Google Scholar 

  11. Parhi, K.K.: Algorithm transformation techniques for concurrent processors. Proc. IEEE 77(12), 1879–1895 (1989)

    Article  Google Scholar 

  12. Gustafsson, O., Wanhammar, L.: Basic arithmetic circuits. In: Meher, P.K., Stouraitis, T. (eds.) Arithmetic Circuits for DSP Applications. Wiley-IEEE Press (2017)

    Google Scholar 

  13. Chang, C.-H., Gustafsson, O., Vinod, A.-P., Faust, M.: Shift-add circuits for multiplications. In: Meher, P.K., Stouraitis, T. (eds.) Arithmetic Circuits for DSP Applications. Wiley-IEEE Press (2017)

    Google Scholar 

  14. Chang, T.L.: Suppression of limit cycles in digital filters designed with one magnitude truncation quantizer. IEEE Trans. Circuits Syst. 28(2), 107–111 (1981)

    Article  Google Scholar 

  15. Dempster, A.G., Macleod. M.D., Gustafsson, O.: Comparison of graphical and sub-expression elimination methods for design of efficient multipliers. In: Asilomar Conference on Signals, Systems and Computers, pp. 72–76, Monterey, CA, 7–10 Nov 2004

    Google Scholar 

  16. Gustafsson, O., Johansson, H., Wanhammar, L.: An MILP approach for the design of linear-phase FIR filters with minimum number of signed-power-of- two terms. In: Proceedings of European Conference on Circuit Theory Design, pp. 28–31, Espoo, Finland, 28–31 Aug 2001

    Google Scholar 

  17. Gustafsson, O., Wanhammar, L.: Design of linear-phase FIR filters combining subexpression sharing with MILP. In: Midwest Symposium on Circuits and Systems, Tulsa, OK, vol. 3, pp. 9–12, 4–7 Aug 2002

    Google Scholar 

  18. Gustafsson, O., Dempster, A.G., Wanhammar, L.: Extended results for minimum-adder constant integer multipliers. In: IEEE International Symposium on Circuits and Systems, vol. 1, pp. 73–76, Phoenix, AZ, 26–29 May 2002

    Google Scholar 

  19. Johansson, K., Gustafsson, O., Wanhammar, L.: A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity. In: European Conference on Circuit Theory Design, vol. 3, pp. 465–468, Cork, Ireland, 29 Aug–1 Sept 2005

    Google Scholar 

  20. Martinez-Peiro, M., Wanhammar, L.: High-speed low-complexity FIR filter using multiplier block reduction and polyphase decomposition. In: Proceedings of IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, vol. 3, pp. 367–370, May 2000

    Google Scholar 

  21. Martinez-Peiro, M., Boemo, E., Wanhammar, L.: Design of high speed multiplierless filters using a nonrecursive signed common subexpression algorithm. IEEE Trans. Circuits Syst. Part II 49(3), 196–203 (2002)

    Article  Google Scholar 

  22. Dempster, A.G., Macleod, M.D.: Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Trans. Circuits Syst. Part II 42(9), 569–577 (1995)

    Article  Google Scholar 

  23. Gustafsson, O., Dempster, A.G., Johansson, K., Macleod, M.D., Wanham-mar, L.: Simplified design of constant coefficient multipliers. Circuits Syst. Signal Process. 25(2), 225–251 (2006)

    Article  MathSciNet  Google Scholar 

  24. Gustafsson, O.: Lower bounds for constant multiplication problems. IEEE Trans. Circuits Syst. Part II 54(11), 974–978 (2007)

    Article  Google Scholar 

  25. Gustafsson, O., Wanhammar, L.: A novel approach to multiple constant multiplication using minimum spanning trees. In: Proceedings of IEEE Midwest Symposium on Circuits and Systems, Tulsa, OK, vol. 3, pp. 652–655, 4–7 Aug 2002

    Google Scholar 

  26. Gustafsson, O., Wanhammar, L.: ILP modelling of the common subexpression sharing problem. In: Proceedings of IEEE Conference on Electronics, Circuits and Systems, vol. 3, pp. 1171–1174, Dubrovnik, Croatia, 12–15 Sept 2002

    Google Scholar 

  27. Hartley, R.I.: Subexpression sharing in filters using canonic signed digit multipliers. IEEE Trans. Circuits Syst. Part II 43, 677–688 (1996)

    Article  Google Scholar 

  28. Potkonjak, M., Srivastava, M.B., Chandrakasan, A.P.: Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Trans. Comput. Aided Des. 15(2), 151–165 (1996)

    Article  Google Scholar 

  29. Nilsson, P.: Arithmetic and architectural design to reduce leakage in nano-scale digital circuits. In: 18th European Conference on Circuit Design, ECCTD-07, Seville, Spain, pp. 372–375

    Google Scholar 

  30. Wanhammar, L.: Design of digital filters with low power consumption. In: 10th European Signal Processing Conference, EUSIPCO, pp. 1–8, 4–8 Sept 2000

    Google Scholar 

  31. Mitra, S.K., Sherwood, R.J.: Digital allpass networks. IEEE Trans. Circuits Syst. 21(5), 688–700 (1974)

    Article  Google Scholar 

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Authors and Affiliations

  1. Linköping University, Linköping, Sweden

    Lars Wanhammar

  2. Tampere University of Technology, Tampere, Finland

    Tapio Saramäki

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  1. Lars Wanhammar
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  2. Tapio Saramäki
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Correspondence to Lars Wanhammar .

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Wanhammar, L., Saramäki, T. (2020). Filter Algorithms. In: Digital Filters Using MATLAB . Springer, Cham. https://doi.org/10.1007/978-3-030-24063-9_3

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  • DOI: https://doi.org/10.1007/978-3-030-24063-9_3

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