Ageing-Aware Logic Synthesis

  • Shengyu Duan
  • Mark Zwolinski
  • Basel HalakEmail author


CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.


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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.The School of Electronics and Computer ScienceUniversity of SouthamptonSouthamptonUK

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