Ageing Mitigation Techniques for SRAM Memories

  • Mohd Syafiq Mispan
  • Mark Zwolinski
  • Basel HalakEmail author


As CMOS technology scales down, ageing-induced negative-bias temperature instability (NBTI) becomes more pronounced. The impact of NBTI on memory elements of digital circuits is crucial, in particular, in static random-access memory (SRAM) as it is always subject to ageing for whatever value is stored in an SRAM cell. Moreover, the prolonged storage of the same bit patterns in an SRAM can cause asymmetric NBTI stress, which is manifested by the threshold voltage drifts of pMOS transistors. These long-term ageing threshold voltage drifts degrade the static noise margin (SNM) of SRAM as memory. The degradation in SNM due to asymmetric NBTI stress can lead to read stability issues and potentially cause failures. Furthermore, the impact of NBTI on SRAM is not only limited to its usage as a memory but also as a hardware security primitive, namely, SRAM physical unclonable function (SRAM-PUF). The random and unique start-up values (SUVs) of SRAM-PUF can be used as a cryptographic key. Nevertheless, asymmetric NBTI stress may cause errors in SUVs. As the error in the SUVs increases resulting in an increasing area overhead of error correction code (ECC) which is needed to generate an error-free cryptographic key. Following the aforementioned reliability issues, this chapter presents two case studies of ageing mitigation techniques for SRAM as memory and PUF, respectively.


  1. 1.
    Mispan, M. S., Halak, B., & Zwolinski, M. (2016). NBTI aging evaluation of PUF- based differential architectures. In: IEEE international symposium on on-line testing and robust system design (pp. 103–108).Google Scholar
  2. 2.
    Gebregiorgis, A., Ebrahimi, M., Kiamehr, S., Oboril, F., Hamdioui, S., & Tahoori, M. B. (2015). Aging mitigation in memory arrays using self-controlled bit-flipping technique. In: Asia and South Pacific design automation conference (pp. 231–236).Google Scholar
  3. 3.
    Guajardo, J., Kumar, S. S., Schrijen, G. J., & Tuyls, P. (2007). FPGA intrinsic PUFs and their use for IP protection. In: International conference on cryptographic hardware and embedded systems (pp. 63–80).Google Scholar
  4. 4.
    Holcomb, D. E., Burleson, W. P., & Fu, K. (2009). Power-Up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Transactions on Computers, 58(9), 1198–1210.MathSciNetCrossRefGoogle Scholar
  5. 5.
    Kohnhäuser, F., Schaller, A., & Katzenbeisser, S. (2015). PUF-based software protection for low-end embedded devices. In M. Conti, M. Schunter, & I. Askoxylakis (Eds.), Trust and trustworthy computing (pp. 3–21). Berlin, Germany: Springer International Publishing.CrossRefGoogle Scholar
  6. 6.
    Schaller, A., Arul, T., Van Der Leest, V., & Katzenbeisser, S. (2014). Lightweight anti- counterfeiting solution for low-end commodity hardware using inherent PUFs. InTrust and trustworthy computing (pp. 83–100). Heidelberg: Springer International Publishing.CrossRefGoogle Scholar
  7. 7.
    Mispan, M. S., Duan, S., Zwolinski, M., & Halak, B. (2018). A reliable PUF in a dual function SRAM. In: International symposium on power and timing modeling, optimization and simulation (pp. 76–81).Google Scholar
  8. 8.
    Simons, P., Van Der Sluis, E., & Van Der Leest, V.. (2012). Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs. In: IEEE international symposium on hardware-oriented security and trust (pp. 7–12).Google Scholar
  9. 9.
    Calimera, A., Macii, E., & Poncino, M. (2010). Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. In: IEEE international symposium on circuits and systems (pp. 785–788).Google Scholar
  10. 10.
    Mostafa, H., Anis, M., & Elmasry, M. (2011). Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(12), 2859–2871.MathSciNetCrossRefGoogle Scholar
  11. 11.
    Faraji, R., & Naji, H. R. (2014). Adaptive technique for overcoming performance degradation due to aging on 6T SRAM Cells. IEEE Transactions on Device and Materials Reliability, 14(4), 1031–1040.CrossRefGoogle Scholar
  12. 12.
    Hoffman, C., Cortes, M., Aranha, D. F., & Araujo, G. (2015). Computer security by hardware-intrinsic authentication. In: International conference on hardware/-software codesign and system synthesis (pp. 143–152).Google Scholar
  13. 13.
    Bacha, A., & Teodorescu, R. (2015). Authenticache: Harnessing cache ECC for system authentication. In: International symposium on microarchitecture (pp. 128–140).Google Scholar
  14. 14.
    Leest, V. V. D., Maes, R., Pim, G. J. S., & Tuyls, P. (2014). Hardware intrinsic security to protect value in the mobile market. In: Information security solutions Europe (pp. 188–198).Google Scholar
  15. 15.
    Rahman, M. T., Rahman, F., Forte, D., & Tehranipoor, M. (2016). An aging-resistant RO-PUF for reliable key generation. IEEE Transactions on Emerging Topics in Computing, 4(3), 335–348.Google Scholar
  16. 16.
    Lao, Y., Yuan, B., Kim, C. H., & Parhi, K. K. (2017). Reliable PUF-based local authenti- cation with self-correction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(2), 201–213.CrossRefGoogle Scholar
  17. 17.
    Mispan, M. S. (2018). Towards reliable and secure physical unclonable functions. Ph.D. thesis, University of Southampton.Google Scholar
  18. 18.
    Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2006). Impact of NBTI on SRAM read stability and design for reliability. In: International symposium on quality electronic design (pp. 210–218).Google Scholar
  19. 19.
    Duan, S., Halak, B., & Zwolinski, M. (2018). Cell flipping with distributed refresh for cache ageing minimization. In: IEEE Asian test symposium (pp. 1–6).Google Scholar
  20. 20.
    Duan, S., Halak, B., Wong, R., & Zwolinski, M. (2016). NBTI lifetime evaluation and extension in instruction caches. In: Workshop on early reliability modeling for aging and variability in silicon systems (pp. 9–12).Google Scholar

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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • Mohd Syafiq Mispan
    • 1
    • 2
  • Mark Zwolinski
    • 1
  • Basel Halak
    • 1
    Email author
  1. 1.The School of Electronics and Computer ScienceUniversity of SouthamptonSouthamptonUK
  2. 2.Micro & Nano Electronics (MiNE), Centre for Telecommunication Research & Innovation (CeTRI)Fakulti Teknologi Kejuruteraan Elektrik & Elektronik, Universiti Teknikal Malaysia MelakaMelakaMalaysia

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