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The Effects of Ageing on the Reliability and Performance of Integrated Circuits

  • Daniele RossiEmail author
Chapter
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Abstract

Bias temperature instability (BTI) is recognised as the primary parametric failure mechanism in nanometre integrated circuits (ICs). Due to the BTI-induced increase in transistor threshold voltage, circuit performance can degrade noticeably over time. If this induced performance degradation exceeds circuit time margins, it may lead to circuit failure and reduce lifetime of electronic systems. In addition, IC susceptibility to soft errors induced by energetic particles is aggravated by BTI ageing, and so resilience of circuits initially robust against these events decreases over time. In order to assess the impact of BTI ageing on IC reliability, it is of utmost importance to evaluate its impact on both IC performance degradation and soft error rate. This chapter describes methodologies to evaluate BTI ageing accurately and presents results on its impact on performance and soft error rate of combinational circuits and storage elements. The presented results can help designers make the right choices when they are called to design ICs featuring high reliability for their whole lifetime.

References

  1. 1.
    Kang, K., Park, S. P., Roy, K., & Alam, M. A. (2007). Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. In: 2007 IEEE/ACM international conference on computer-aided design (pp. 730–734). San Jose, CA.Google Scholar
  2. 2.
    Chandra, V.(2014, June). Monitoring reliability in embedded processors – A multilayer view. In: Design automation conference (DAC) (pp. 1–6).Google Scholar
  3. 3.
    Henkel, J., Bauer, L., Zhang, H., Rehman, S. & Shafique, M.(2014). Multi-layer dependability: From microarchitecture to application level. In: 2014 51st ACM/EDAC/IEEE design automation conference (DAC) (pp. 1–6). San Francisco, CA.Google Scholar
  4. 4.
    Alam, M. A., Kufluoglua, H., Varghese, D., & Mahapatra, S. (2007). A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectronics Reliability, 47(6), 853–862.CrossRefGoogle Scholar
  5. 5.
    Joshi, K., Mukhopadhyay, S., Goel, N. & Mahapatra, S. (2012). A consistent physical framework for N and P BTI in HKMG MOSFETs. 2012 IEEE international reliability physics symposium (IRPS) (pp. 5A.3.1–5A.3.10). Anaheim, CA.Google Scholar
  6. 6.
    Liu, C., Kochte, M. A., & Wunderlich, H. J.(2015, July). Efficient observation point selection for aging monitoring. In: On-line testing symposium (IOLTS), 2015 IEEE 21st international (pp. 176–181).Google Scholar
  7. 7.
    Agarwal, M., Paul, B. C., Zhang, M., & Mitra, S. Circuit failure prediction and its application to transistor aging. In: Proceedings of IEEE VLSI test symposium (pp. 277–286).Google Scholar
  8. 8.
    Wang, W., Wei, Z., Yang, S., & Cao, Y. An efficient method to identify critical gates under circuit aging. In: Proceedings of IEEE/ACM international conference on computer-aided design (pp. 735–740).Google Scholar
  9. 9.
    Vazquez, J. C., Champac, V., Ziesemer, A. M., Reis, R., Semiao, J., & Teixeira, I. C. Predictive error detection by on-line aging monitoring. In: Proceedings of IEEE international on-line testing symposium (pp. 9–14).Google Scholar
  10. 10.
    Baranowski, R., Firouzi, F., Kiamehr, S., Liu, C., Tahoori, M., & Wunderlich, H. (2015). On-line prediction of NBTI-induced aging rates. In 2015 Design, automation & test in Europe conference & exhibition (pp. 589–592). Grenoble: DATE.Google Scholar
  11. 11.
    Chahal, H., Tenentes, V., Rossi, D., & Al-Hashimi, B. M. BTI aware thermal management for reliable DVFS designs. In Proceeding of 29th IEEE symposium on defect and fault tolerance in VLSI and nanotechnology systems (pp. 1–6). Connecticut: The University of Connecticut in Storrs.Google Scholar
  12. 12.
    Baumann, R. C. (2005). Radiation-induced soft-errors in advanced semiconductor technologies. IEEE Transactions on Device and Materials Reliability, 5(3), 305–316.CrossRefGoogle Scholar
  13. 13.
    Seifert, N., Gill, B., Zia, V., Zhang, M., & Ambrose, V. (2007). On the scalability of redundancy based SER mitigation schemes. In: Proceedings of international conference on integrated circuit design and technology.Google Scholar
  14. 14.
    Cannon, E. H., Klein Osowski, A., Kanj, R., Reinhardt, D. D., & Joshi, R. V. (2008). The impact of aging effects and manufacturing variation on SRAM soft-error rate. IEEE Transactions on Device and Materials Reliability, 8(1), 145–152.CrossRefGoogle Scholar
  15. 15.
    Ramakrishnan, K., Rajaraman, R., Suresh, S., Vijaykrishnan, N., Xie, Y., & Irwin, M. J. Variation impact on SER of combinational circuits. In: Proceedings of international symposium on quality electronic design (pp. 911–916).Google Scholar
  16. 16.
    Rossi, D., Omaña, M., Metra, C., & Paccagnella, A. (2011). Impact of aging phenomena on soft error susceptibility. In: Proceedings of IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (pp. 18–24).Google Scholar
  17. 17.
    Harada, R., Mitsuyama, Y., Hashimoto, M., & Onoye, T. (2013). Impact of NBTI-induced pulse-width modulation on SET pulse-width measurement. IEEE Transactions on Nuclear Science, 60(4), 2630–2634.CrossRefGoogle Scholar
  18. 18.
    Rossi, D., Omaña, M., Metra, C., & Paccagnella, A. (2015). Impact of Bias temperature instability on soft error susceptibility. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(4), 743–751.CrossRefGoogle Scholar
  19. 19.
    Omaña, M., Rossi, D., Edara, T., & Metra, C. (2016). Impact of aging phenomena on latches’ robustness. IEEE Transactions on Nanotechnology, 15(2), 129–136.CrossRefGoogle Scholar
  20. 20.
    Chakravarthi, S., Krishnan, A., Reddy, V., Machala, C. F. & Krishnan, S. A comprehensive framework for predictive modeling of negative bias temperature instability. 2004 IEEE international reliability physics symposium. Proceedings (pp. 273–282). Phoenix, AZ.Google Scholar
  21. 21.
    Agarwal, M., Balakrishnan, V., Bhuyan, A., Kim, K., Paul, B. C., Wang, W., Yang, B., Cao, Y., & Mitra, S. Optimized circuit failure prediction for aging: Practicality and promise. In: Proceedings of IEEE international test conference (pp. 1–10).Google Scholar
  22. 22.
    Yang, H.-I., Hwang, W., & Chuang, C.-T. (2011). Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high-\kappa metal-gate devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(7), 1192–1204.CrossRefGoogle Scholar
  23. 23.
    Toledano-Luque, M., Kaczer, B., Franco, J., Roussel, P. J., Grasser, T., Hoffmann, T. Y., & Groeseneken, G.(2011). From mean values to distribution of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation. In: 2011 symposium on VLSI technology, digest of technical papers (pp. 152–153).Google Scholar
  24. 24.
    Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2003). Digital integrated circuits (2nd ed.). Pearson – Prentice Hall.Google Scholar
  25. 25.
    Reddy, V. et al. (2002). Impact of negative bias temperature instability on digital circuit reliability. 2002 IEEE International reliability physics symposium. Proceedings. 40th annual (Cat. No. 02CH37320) (pp. 248–254). Dallas, TX.Google Scholar
  26. 26.
    Krishnan, A. T., Reddy, V., Chakravarthi, S., Rodriguez, J., John, S. & Krishnan, S. NBTI impact on transistor and circuit: Models, mechanisms and scaling effects [MOSFETs]. IEEE international electron devices meeting 2003 (pp. 14.5.1–14.5.4). Washington, DC.Google Scholar
  27. 27.
    Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., & Roy, K. (2005). Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron Device Letters, 26(8), 560–562.CrossRefGoogle Scholar
  28. 28.
    Rossi, D., Tenentes, V., Yang, S., Khursheed, S., & Al-Hashimi, B. M. (2017). Aging benefits in nanometer CMOS designs. IEEE Transactions on Circuits and Systems II – Express Brief, 64(3), 324–328.CrossRefGoogle Scholar
  29. 29.
    Predictive technology model (PTM), http://www.ptm.asu.edu.
  30. 30.
    Bagatin, M., Gerardin, S., Paccagnella, A., & Faccio, F. (2010). Impact of NBTI aging on the single-event upset of SRAM cells. IEEE Transactions on Nuclear Science, 57(6), 3245–3250.Google Scholar
  31. 31.
    Lin, C. Y. H., Huang, R., Wen, C., & Chang, A.(2013). Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs. In: Proceedings of IEEE international symposium on VLSI design, automation, and test (VLSI-DAT).Google Scholar
  32. 32.
    Mavis, D. G., & Eaton, P. H. (2007). SEU and SET modeling and mitigation in deep submicron technologies. Proceedings of annual IEEE international reliability physics symposium (pp. 293–305).Google Scholar
  33. 33.
    Karnik, T., & Hazucha, P. (2004). Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Transactions on Dependable and Secure Computing, 1(2), 128–143.CrossRefGoogle Scholar
  34. 34.
    Benedetto, J. M., Eaton, P. H., Mavis, D. G., Gadlage, M., & Turflinger, T. (2006). Digital single event transient trends with technology node scaling. IEEE Transactions on Nuclear Science, 53(6), 3462–3465.CrossRefGoogle Scholar
  35. 35.
    Tosaka, Y., et al. (1998). Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits. IEEE Transactions on Electron Devices, 45(7), 1453–1458.CrossRefGoogle Scholar
  36. 36.
    Mahatme, N. N. et al. (2014) Impact of technology scaling on the combinational logic soft error rate. 2014 IEEE international reliability physics symposium (pp. 5F.2.1–5F.2.6). Waikoloa, HI.Google Scholar
  37. 37.
    Messenger, G. C. (1982). Collection of charge on junction nodes from ion tracks. IEEE Transactions on Nuclear Science, 29(6), 2024–2031.CrossRefGoogle Scholar
  38. 38.
    Cha, H. & Patel, J. H. A logic-level model for α-particle hits in CMOS circuits. In: Proceedings of IEEE international conference on computer design (pp. 538–542).Google Scholar
  39. 39.
    Heidel, D. F., Rodbell, K. P., Cannon, E. H., Cabral, C., Gordon, M. S., Oldiges, P., & Tang, H. H. K. (2008). Alpha-particle-induced upsets in advanced CMOS circuits and technology. IBM Journal of Research & Development, 52(3), 225–232.CrossRefGoogle Scholar
  40. 40.
    Rossi, D., Cazeaux, J. M., Omaña, M., Metra, C., & Chatterjee, A. (2009). Accurate linear model for SET critical charge estimation. IEEE Transactions on VLSI Systems, 17(8), 1161–1166.CrossRefGoogle Scholar
  41. 41.
    Hazucha, P., & Svensson, C. (2000). Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Transactions on Nuclear Science, 47(6), 2586–2594.CrossRefGoogle Scholar
  42. 42.
    Ramanarayanan, R., Degalahal, V. S., Krishnan, R., Kim, J., Narayanan, V., Xie, Y., Irwin, M. J., & Unlu, K. (2009). Modeling soft errors at the device and logic levels for combinational circuits. IEEE Transactions on Dependable and Secure Computing, 6(3), 202–216.CrossRefGoogle Scholar
  43. 43.
    Omaña, M., Rossi, D., & Metra, C. (2004). Model for transient fault susceptibility of combinational circuits. Journal of Electronic Testing, Theory and Application (JETTA), 20(5), 501–509.CrossRefGoogle Scholar
  44. 44.
    Wang, F., Xie, Y., Rajaraman, R., & Vaidyanathan, B. (2007). Soft error rate analysis for combinational logic using an accurate electrical masking model. In: Proceedings IEEE 20th international conference VLSI design (pp. 165–170).Google Scholar
  45. 45.
    Zhang, M., & Shanbhag, N. R. (2006). Soft-error-rate-analysis (SERA) methodology. IEEE Transactions Computer-Aided Design Integrated Circuits Systems, 25(10), 2140–2155.CrossRefGoogle Scholar
  46. 46.
    Zhang, B., Wang, W.-S., & Orshansky, M. FASER: Fast analysis of soft error susceptibility for cell-based designs. In: Proceedings IEEE 7th international symposium quality electronic design (pp. 755–760).Google Scholar
  47. 47.
    ITC99 Benchmark Home Page [Online]. Available: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html.
  48. 48.
    Nicolaidis, M., Perez, R., & Alexandrescu, D. Low-cost highly-robust hardened cells using blocking feedback transistors. In: Proceedings of IEEE VLSI test symposium (pp. 371–376).Google Scholar
  49. 49.
    Gill, B., Seifert, N., & Zia, V.(2009). Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node. In: Proceedings of IEEE International reliability physics symposium (pp. 199–205).Google Scholar
  50. 50.
    Omaña, M., Rossi, D., & Metra, C. (2007). Latch susceptibility to transient faults and new hardening approach. IEEE Transactions on Computers, 56(9), 1255–1268.MathSciNetCrossRefGoogle Scholar
  51. 51.
    Fan, W., & Agrawal, V. D. Soft error rate determination for nanoscale sequential logic. In: Proceedings of international symposium on quality electronic design (ISQED) (pp. 225–230.Google Scholar
  52. 52.
    Lin, S., Kim, Y-B., & Lombardi, F. Soft-error hardening designs of nanoscale CMOS latches. In: Proceedings of IEEE VLSI test symposium (pp. 41–46).Google Scholar
  53. 53.
    Karnik, T., Vangal, S., Veeramachaneni, V., Hazucha, P., Erraguntla, V., & Borkar, S. Selective node engineering for Chip-level soft error rate improvement. Symposium VLSI circuits, digest technical papers (pp. 204–205).Google Scholar
  54. 54.
    Shirinzadeh, S., & Asli, R. N.(2013). Design and performance evaluation of a low cost full protected CMOS latch. In: Proceedings of IEEE17th CSI international symposium on computer architecture and digital systems (CADS) (pp. 139–141).Google Scholar
  55. 55.
    Omaña, M., Rossi, D., & Metra, C. (2003). Novel transient fault hardened static latch. In: Proceedings of IEEE international test conference (pp. 886–892).Google Scholar
  56. 56.
    Mitra, S., Seifert, N., Zhang, M., Shi, Q., & Kim, K. S. (2005). Robust system design with built-in soft error resilience. IEEE Computer, 38(2), 43–52.CrossRefGoogle Scholar
  57. 57.
    Calin, T., Nicolaidis, M., & Velazco, R. (1996). Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science, 43(6), 2874.CrossRefGoogle Scholar
  58. 58.
    Nan, H., & Ken, C. (2012). High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(7), 1445–1457.MathSciNetCrossRefGoogle Scholar
  59. 59.
    Omaña, M., Rossi, D., & Metra, C. (2010). High performance robust latches. IEEE Transactions on Computers, 59(11), 1455–1465.MathSciNetCrossRefGoogle Scholar
  60. 60.
    Weste, N., & Harris, D. (2004). CMOS VLSI design a circuits and systems perspective. New York: Addison-Wesley.Google Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.University of HertfordshireHatfieldUK

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