The techniques described in this book have immense potential to satisfy the quest for ever increasing power constraint in ultra low power radios for the emerging internet of things and wireless body area networks. The primary impact of these techniques will be on next-generation low power wireless consumer electronics where the data rates will multiply but the power budget for radio will be more constrained demanding longer battery life. Sub-harmonic injection locking is a powerful technique to reduce power consumption of the frequency synthesizer using PLL running at a very low frequency. A higher harmonic may be chosen to run the PLL at even lesser frequency thereby further reducing the power of the synthesizer. This also allows modulation at lower frequency further reducing transmit power consumption. The noise cancelling techniques used in the mixer and LNA are key to achieving low voltage operation of the receiver frontend with excellent figure of merit. Zero power passive voltage gain receiver frontend using a 1:3 balun combined with passive mixer-based downconversion is a simple and robust architecture which allows us to approach the 1 nJ/bit limit for low power transceivers. The digital power amplifier is highly flexible in terms of types of modulation and may be upgraded to encompass broader modulation capabilities for internet of things. Recently, radio standards for internet of things are being drafted for operation at different frequency bands. Although the design and circuit techniques described in this book were for an IEEE 802.15.6 standard compliant radio, much of them may be easily portable to emerging low power standards.