Abstract
A low noise amplifier (LNA) operating at millimeter wave (mmWave) frequency and a down converter suitable for IEEE 802.11ad receiver is designed in a 65 nm radio frequency (RF)-CMOS low leakage (LL) process. These designed blocks are integrated in a super heterodyne receiver architecture and the overall performance of the receiver is analyzed. The designed LNA gives a performance metric of 20 dB of gain, 1.7 dB of noise figure (NF) and −7.78 dBm of IIP3. Modified Gilbert cell topology is used for down converter which gives a conversion gain of 1.5 dB from 57 GHz to 66 GHz, input P1dB of −7.8dBm and IIP3 of 8.78 dBm with RF at 57.24 GHz from a 1.2 V supply voltage and a 1Vpp of local oscillator (LO) drive. The obtained IIP3 is 10.08 dB higher than the conventional Gilbert cell and offers an error vector magnitude (EVM) improvement of −23 dB at the receiver. This work provides RF designers a comprehensive understanding of system and circuit level on pre silicon base.
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Funding
This research work was supported by the Women Scientists Scheme A (WOS-A) SR/WOS-A/ET-82/2016 from Department of Science and Technology (DST), Government of India.
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© 2019 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Pournamy, S., Kumar, N. (2019). System Level Performance Analysis of Designed LNA and Down Converter for IEEE 802.11ad Receiver. In: Kumar, N., Venkatesha Prasad, R. (eds) Ubiquitous Communications and Network Computing. UBICNET 2019. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 276. Springer, Cham. https://doi.org/10.1007/978-3-030-20615-4_2
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DOI: https://doi.org/10.1007/978-3-030-20615-4_2
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