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3D for Efficient FPGA

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Abstract

This chapter covers a unique use of monolithic 3D technologies to improve FPGA design. It presents an FPGA architecture with logic programmable level plus independent routing programmable level. This leads to a futuristic FPGA in which structure and process similar to that of 3D NAND provide FPGA with lower cost and higher density than 2D Standard Cell design.

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  • DOI: 10.1007/978-3-030-18338-7_11
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Correspondence to Zvi Or-Bach .

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Or-Bach, Z. (2020). 3D for Efficient FPGA. In: Murmann, B., Hoefflinger, B. (eds) NANO-CHIPS 2030. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-030-18338-7_11

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