Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications

  • Panagiotis G. MousouliotisEmail author
  • Loukas P. Petrou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11444)


Convolutional neural networks (CNNs) have been successfully used to attack problems such as object recognition, object detection, semantic segmentation, and scene understanding. The rapid development of deep learning goes hand by hand with the adaptation of GPUs for accelerating its processes, such as network training and inference. Even though FPGA design exists long before the use of GPUs for accelerating computations and despite the fact that high-level synthesis (HLS) tools are getting more attractive, the adaptation of FPGAs for deep learning research and application development is poor due to the requirement of hardware design related expertise. This work presents a workflow for deep learning mobile application acceleration on small low-cost low-power FPGA devices using HLS tools. This workflow eases the design of an improved version of the SqueezeJet accelerator used for the speedup of mobile-friendly low-parameter ImageNet class CNNs, such as the SqueezeNet v1.1 and the ZynqNet. Additionally, the workflow includes the development of an HLS-driven analytical model which is used for performance estimation of the accelerator.


FPGA accelerator High-level synthesis Mobile embedded systems CNN Deep learning application 


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Authors and Affiliations

  1. 1.Division of Electronics and Computer Engineering, Department of Electrical and Computer Engineering, Faculty of EngineeringAristotle University of ThessalonikiThessalonikiGreece

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