Abstract
The work, presented in this paper has been carried out within an EU-funded project with the name EXTRA, aimed at creating an environment to generate, configure and evaluate user-customizable Coarse-Grained Reconfigurable Array (CGRA) architectures, called VCGRA. The tools provide a fully automatic development and evaluation platform for a VCGRA architecture including synthesis and execution of the VCGRA with its corresponding hardware configuration and the required interfaces on an FPGA platform. Furthermore, it also provides the necessary software modules for data transmission between the processing system (PS) and the VCGRA on reconfigurable hardware. In this paper, the part of the “VCGRA Toolflow” which is responsible to provide the generation of the VCGRA hardware’s FPGA-bitstream from a specification is discussed. Especially the generation of the VCGRA hardware, the automatic creation of the required interfaces and the evaluation of the improvements are presented. The toolflow is planned to be an open source project, providing hardware developers with a framework to create extensions for the VCGRA architecture, and to make them accessible for software developers. Many aspects of the hardware can be customized, including the functions provided by the Processing Elements and the communication infrastructure as well as the target platform integration. Furthermore, software developers from the EDA domain are enabled to provide, integrate and evaluate algorithms for application mapping.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Brant, A., Lemieux, G.G.F.: ZUMA: an open FPGA overlay architecture. In: 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp. 93–96, April 2012. https://doi.org/10.1109/FCCM.2012.25
Capalija, D., Abdelrahman, T.S.: A high-performance overlay architecture for pipelined execution of data flow graphs. In: 2013 23rd International Conference on Field programmable Logic and Applications, pp. 1–8, September 2013. https://doi.org/10.1109/FPL.2013.6645515
Coole, J., Stitt, G.: Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. In: 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 13–22, October 2010. https://doi.org/10.1145/1878961.1878966
Fricke, F., Werner, A., Shahin, K., Huebner, M.: CGRA tool flow for fast run-time reconfiguration. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P.C. (eds.) ARC 2018. LNCS, vol. 10824, pp. 661–672. Springer, Cham (2018). https://doi.org/10.1007/978-3-319-78890-6_53
Hartenstein, R.: Coarse grain reconfigurable architecture (embedded tutorial). In: Proceedings of the 2001 Asia and South Pacific Design Automation Conference, ASP-DAC 2001, pp. 564–570. ACM, New York (2001)
Heyse, K., Davidson, T., Vansteenkiste, E., Bruneel, K., Stroobandt, D.: Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS. In: 2013 23rd International Conference on Field programmable Logic and Applications, pp. 1–8, September 2013
Jain, A.K., Maskell, D.L., Fahmy, S.A.: Throughput oriented FPGA overlays using DSP blocks. In: 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1628–1633, March 2016
Kulkarni, A., Stroobandt, D.: How to efficiently reconfigure tunable lookup tables for dynamic circuit specialization. Int. J. Reconfigurable Comput. 2016, 1–12 (2016)
Lee, D., Jo, M., Han, K., Choi, K.: FloRA: coarse-grained reconfigurable architecture with floating-point operation capability. In: International Conference on Field-Programmable Technology, FPT 2009, pp. 376–379, December 2009
Shukla, S., Bergmann, N.W., Becker, J.: QUKU: a two-level reconfigurable architecture. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI 2006), pp. 6-pp, March 2006. https://doi.org/10.1109/ISVLSI.2006.76
Stitt, G., Coole, J.: Intermediate fabrics: virtual architectures for near-instant FPGA compilation. IEEE Embedded Syst. Lett. 3(3), 81–84 (2011). https://doi.org/10.1109/LES.2011.2167713
Thomas, A., Rückauer, M., Becker, J.: HoneyComb: a multi-grained dynamically reconfigurable runtime adaptive hardware architecture. In: 2011 IEEE International SOC Conference (SOCC), pp. 335–340, September 2011
Vansteenkiste, E., Al Farisi, B., Bruneel, K., Stroobandt, D.: TPaR: place and route tools for the dynamic reconfiguration of the FPGA’s interconnect network. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 33(3), 370–383 (2014)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Werner, A., Fricke, F., Shahin, K., Werner, F., Hübner, M. (2019). Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms. In: Hochberger, C., Nelson, B., Koch, A., Woods, R., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2019. Lecture Notes in Computer Science(), vol 11444. Springer, Cham. https://doi.org/10.1007/978-3-030-17227-5_20
Download citation
DOI: https://doi.org/10.1007/978-3-030-17227-5_20
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-17226-8
Online ISBN: 978-3-030-17227-5
eBook Packages: Computer ScienceComputer Science (R0)