UltraSynth: Integration of a CGRA into a Control Engineering Environment

  • Dennis WolfEmail author
  • Tajas Ruschke
  • Christian Hochberger
  • Andreas Engel
  • Andreas Koch
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11444)


Coarse Grained Reconfigurable Arrays (CGRAs) can exploit parallelism of compute-intense applications by distributing their workload across a set of Processing Elements (PEs). They are highly efficient in computation and flexible due to their reconfigurability. While these attributes make CGRAs highly interesting as general purpose hardware accelerators, their incorporation into a complete computing system raises severe challenges at the hardware and software level. To overcome the stage of a simulated concept, CGRAs need to be applied to the real-world in order to demonstrate the practicability of the overall system. This paper presents the integration of a CGRA into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC). It focuses on the fully automated tool-chain mapping abstract engineering models to CGRA configurations, and on the SoC-internal runtime communication on hardware level.



This research was funded by the German Federal Ministry for Education and Research with the funding ID 01 IS 15020 and supported by iXtronics.


  1. 1.
    Cong, J., Huang, H., Ma, C., Xiao, B., Zhou, P.: A fully pipelined and dynamically composable architecture of CGRA. In: IEEE International Symposium on Field-Programmable Custom Computing Machines, pp. 9–16 (2014)Google Scholar
  2. 2.
    dSpace: DS5203 - FPGA programmable per application (2018)Google Scholar
  3. 3.
    Fathoni, M.F., Wuryandari, A.I.: Comparison between Euler, Heun, Runge-Kutta and Adams-Bashforth-Moulton integration methods in the particle dynamic simulation. In: International Conference on Interactive Digital Media, pp. 1–7, December 2015Google Scholar
  4. 4.
    Fricke, F., Werner, A., Shahin, K., Huebner, M.: CGRA tool flow for fast run-time reconfiguration. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P.C. (eds.) ARC 2018. LNCS, vol. 10824, pp. 661–672. Springer, Cham (2018). Scholar
  5. 5.
    Ho, C.H., et al.: Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation. Energy (mJ) 5(10), 15 (2015)Google Scholar
  6. 6.
    iXtronics: Mechatronics, tools & technologies.
  7. 7.
    Lee, D., Jo, M., Han, K., Choi, K.: FloRA: coarse-grained reconfigurable architecture with floating-point operation capability. In: International Conference on Field-Programmable Technology, pp. 376–379, December 2009.
  8. 8.
    Ruschke, T., Jung, L., Hochberger, C.: A near optimal integrated solution for resource constrained scheduling, binding and routing on CGRAs. In: IEEE International Parallel and Distributed Processing Symposium Workshops, pp. 213–218 (2017)Google Scholar
  9. 9.
    Ruschke, T., Jung, L., Wolf, D., Hochberger, C.: Scheduler for inhomogeneous and irregular CGRAs with support for complex control flow. In: IEEE International Parallel and Distributed Processing Symposium Workshops, pp. 198–207, May 2016Google Scholar
  10. 10.
    Wolf, D., Ruschke, T., Hochberger, C.: Amidar project: lessons learned in 15 years of researching adaptive processors. In: International Symposium on Reconfigurable Communication-centric Systems-on-Chip, July 2018Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Dennis Wolf
    • 1
    Email author
  • Tajas Ruschke
    • 1
  • Christian Hochberger
    • 1
  • Andreas Engel
    • 2
  • Andreas Koch
    • 2
  1. 1.Computer Systems Group (RS)TU DarmstadtDarmstadtGermany
  2. 2.Embedded Systems and Applications Group (ESA)TU DarmstadtDarmstadtGermany

Personalised recommendations