Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging

  • Helena Cruz
  • Rui Policarpo DuarteEmail author
  • Horácio Neto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11444)


In this research work, an on-board dual-core embedded architecture was developed for SAR imaging systems, implementing a reduced-precision redundancy fault-tolerance mechanism. This architecture protects the execution of the BackProjection Algorithm, capable of generating acceptable SAR images in embedded systems subjected to errors from the space environment. The proposed solution was implemented on a Xilinx SoC device with a dual-core processor. The present work was able to produced images with less 0.65 dB on average, than the fault-free image, at the expense of a time overhead up to 33%, when in the presence of error rates similar to the ones measured in space environment. Notwithstanding, the BackProjection algorithm executed up to 1.58 times faster than its single-core version without any fault-tolerance mechanisms.


Synthetic-Aperture Radar BackProjection Algorithm Approximate computing FPGA Dual-core SoC 


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© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.INESC-IDLisbonPortugal
  2. 2.Instituto Superior TécnicoUniversity of LisbonLisbonPortugal

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