An FPGA Based Hardware Accelerator for Classification of Handwritten Digits

  • R. Gautham Sundar RamEmail author
  • Nitin Chaturvedi
  • Sumeet Saurav
  • Sanjay Singh
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 940)


Over the past few years, Convolutional Neural Networks (CNNs) have provided major breakthroughs in fields such as computer vision and natural language processing, resulting in a rise in the adoption of CNNs with increased levels of complexity. Consequently, the need for fast and power efficient processing of such networks has become critically important. Conventional hardware solutions, namely CPUs and GPUs, fail to address these requirements as CPUs are not suited for processing massively parallel multiply and accumulate (MAC) operations and GPUs are not power efficient. However, Field Programmable Gate Arrays (FPGAs) have emerged as a promising alternative due to their extensive programmability, ease of executing parallel operations and wide interfacing capabilities. In this paper, we have designed a hardware accelerator for speeding up the inference phase of LeNet–5 to enable faster classification of handwritten digits. We employ software quantization for ease of implementation on FPGAs, and partial pipelining to process the various layers of a typical CNN. Targeting the Xilinx Zynq-7000 SoC, we report a speedup improvement of at least 4.7x and power efficiency improvement of 32x compared to similar works.


FPGA CNN Accelerator LeNet–5 


  1. 1.
    Steinkraus, D., Buck, I., Simard, P. Y.: Using GPUs for machine learning algorithms. In: Eighth International Conference on Document Analysis and Recognition (ICDAR 2005), Seoul, South Korea, vol. 2, pp. 1115-1120 (2005).
  2. 2.
    Bertend: GPU vs FPGA Performance Comparison.
  3. 3.
    Qiao, Y., Shen, J., Xiao, T., Yang, Q., Wen, M., Zhang, C.: FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29(20) (2017). Scholar
  4. 4.
    Kiningham, K., Graczyk, M., Ramkumar, A.: Design and analysis of a hardware CNN accelerator. Technical report, Stanford University (2017)Google Scholar
  5. 5.
    Guo, K., Han, S., Yao, S., Wang, Y., Xie, Y., Yang, H.: Software-Hardware codesign for efficient neural network acceleration. IEEE Micro 37(2), 18–25 (2017)CrossRefGoogle Scholar
  6. 6.
    Chakradhar, S., Sankaradas, M., Jakkula, V., Cadambi S.: A dynamically configurable coprocessor for convolutional neural networks. In: ACM SIGARCH Computer Architecture News, pp. 247–257, vol. 38, no. 3. ACM (2010)Google Scholar
  7. 7.
    LeCun, Y., Bottou, L., Bengio, Y., Haffner, P.: Gradient-based learning applied to document recognition. Proc. IEEE 86(11), 2278–2324 (1998)CrossRefGoogle Scholar
  8. 8.
    Jia, Y., Shelhamer, E., Donahue, J., Karayev, S., Long, J., Girshick, R., Guadarrama, S., Darrell, T.: Caffe: convolutional architecture for fast feature embedding. In: Proceedings of the 22nd ACM International Conference on Multimedia, pp. 675–678. ACM (2014)Google Scholar
  9. 9.
    Zhou, Y., Jiang, J.: An FPGA-based accelerator implementation for deep convolutional neural networks. In: 2015 4th International Conference on Computer Science and Network Technology (ICCSNT), pp. 829–832 (2015).
  10. 10.
    Mujawar, S., Kiran, D., Ramasangu, H.: An efficient CNN architecture for image classification on FPGA accelerator. In: Second International Conference on Advances in Electronics, Computers and Communications (ICAECC), pp. 1–4. IEEE (2018).
  11. 11.
    Ghaffari, S., Sharifian, S.: FPGA-based convolutional neural network accelerator design using high level synthesize. In: 2nd International Conference of Signal Processing and Intelligent Systems (ICSPIS), pp. 1–6 (2016).

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  • R. Gautham Sundar Ram
    • 1
    Email author
  • Nitin Chaturvedi
    • 1
  • Sumeet Saurav
    • 2
  • Sanjay Singh
    • 2
  1. 1.Department of EEEBirla Institute of Technology and SciencePilaniIndia
  2. 2.Cognitive Computing GroupCSIR-CEERIPilaniIndia

Personalised recommendations