Abstract
Arithmetic Logic Unit (ALU) are main constructing block of several digital computation systems like digital calculator, mobile phone, high computational computer, Digital signal processors etc. In current scenario electronic market as technology is raising every day, Fast rising technologies with handy devices demands for low power VLSI design. Ultimatum design with less delay, low power and low area is increasing. Reversible logic gates are suitable to minimize the power dissipation in the circuit, designed reversible logic is suitable. ALU design is intended with both reversible logic gates and irreversible logic gates to reduce dissipation, switching power and delay. The proposed type of design are said to be Hybrid ALU architecture. In arithmetical adder, time taken to propagate carry are minimized by using KSA and CSA, BEC is used to minimize area instead of Ripple Carry Adder. Adder design are utilized to add partial products in Vedic-multiplier, which minimizes delay in digital multiplier.
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Shirol, S.B., Ramakrishna, S., Shettar, R.B. (2020). A Novel Design and Implementation of 8-Bit and 16-Bit Hybrid ALU. In: Abraham, A., Cherukuri, A.K., Melin, P., Gandhi, N. (eds) Intelligent Systems Design and Applications. ISDA 2018 2018. Advances in Intelligent Systems and Computing, vol 940. Springer, Cham. https://doi.org/10.1007/978-3-030-16657-1_4
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DOI: https://doi.org/10.1007/978-3-030-16657-1_4
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