There are several analog-to-digital converter architectures described in the literature that implement a nonlinear conversion characteristic. This chapter presents an overview of the different architectures and how the nonlinear characteristic is achieved and summarizes the state-of-the-art for each of the architectures. Most of the architectures described in the following sections can be used to implement arbitrary nonlinear transfer characteristics, however most of the examples found in the literature show logarithmic transfer functions. For the same conversion resolution, a logarithmic converter can attain a larger input dynamic range than a linear converter, conversely for linear and logarithmic converters with a similar input dynamic range, the logarithmic converter will attain a smaller signal to noise ratio. Figure 2.1 shows an example of a conversion result of a sinusoidal signal by converters with different conversions characteristics. On the left, the conversion result for a linear converter shows a constant quantization step while for the other two converters the quantization step is not constant. The floating-point converter is characterized by having zones with a constant quantization step, with the quantization step being different from zone to zone. The logarithmic converter on the other hand does not have a fixed quantization step like the linear converter, or zones where the quantization step is fixed like in the floating-point converter. In the logarithmic converter the quantization step increases progressively from a small quantization step for small input signals to a large quantization step for large input signals.

Fig. 2.1
figure 1

Examples of conversion results of a sinusoidal signal by converters: a linear ADC, b floating point ADC, c logarithmic ADC

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2.1 Floating Point Converters

Floating point converters owe their name to the way the digital code is encoded. The digital code is composed of a fixed resolution part and an exponent part, much like the encoding used in floating point numbers. As a derivation of the linear two step architecture the working principle is similar. In the first quantization step the exponent is resolved and in a second step the mantissa is resolved. The two results are combined into a single digital code which can be composed of exponent plus mantissa, or it can be a normalized binary code obtained by shifting the mantissa and adding an offset correction. The amounts of shifting and offset correction to add are dependent on the exponent value.

Figure 2.2 shows a general block diagram of the floating-point converter. Each sample is acquired and digitized by the flash ADC of the first stage that directly determines the exponent.

Fig. 2.2
figure 2

Floating point converter block diagram

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The gain of the variable gain amplifier (VGA) will be set according to the value of the exponent. The second conversion step digitizes the amplified voltage at the output of the VGA and obtains the mantissa. The two results are then combined to form the digital output code. This is the approach followed in [1]. An alternative approach is to combine the VGA with the mantissa ADC. This is possible if a pipeline ADC is used [2]. In this case the first few pipeline stages act as a VGA and typical pipeline stages. If the input signal level is high, the first stages will act as typical pipeline stages, if the input signal level is low then the first stages will apply more gain and perform the function of the VGA.

The exponent and mantissa can be only joined if a compact digital representation of the input signal is desired. However, this representation will need to be translated into a binary weighted digital code at some point. If this translation is performed in the ADC, the exponent value obtained in the first conversion step is fed to a ROM, which contains the information of how many bits the mantissa needs to be shifted and the offset correction to be added, as exemplified in the output logic section of Fig. 2.2.

For simplicity, the gains used in the VGA should be a power of two. This allows the determination of the output code using only shifts and sums as illustrated in Fig. 2.2. The gains used do not need to be the consecutive powers of two.

The maximum signal-to-noise ratio achievable is determined by the resolution of the mantissa ADC, the maximum SNR is given by:

$$SNR_{dB} = 6.02N_{2} + 1.76$$
(2.1)

where N2 is the resolution in bits of the linear ADC that determines the mantissa.

The dynamic range of a floating-point converter is higher than that of a linear converter of N2 bit, this is due to the usage of a VGA to amplify the input signal when needed. The dynamic range for a floating-point converter is given by:

$$DR_{dB} = 20\log_{10} (2^{{\left( {\log_{2} Gain_{\text{max}} + N_{2} } \right)}} - 1)$$
(2.2)

where Gainmax is the maximum gain provided by the VGA.

For a single ended floating point converter the output code is given by:

$$Code = \frac{Vin \cdot Gain}{Vref} \cdot 2^{{N_{2} }} \ll \log_{2} \frac{{Gain_{\text{max}} }}{Gain}$$
(2.3)

where Vin is the input voltage, Gain is the gain applied by the VGA stages for the given input voltage, Gainmax is the maximum gain provided by the VGA stages, Vref is the reference voltage used by the ADC and N2 is the number of bits of ADC that determines the mantissa.

Figure 2.3 shows a Matlab simulation result, comparing 10 bit and 15 bit linear converters with a floating point converter with a 10 bit mantissa and 5 bit dynamic range extension. This figure shows that for smaller amplitude input signals the SNR is the same as for a 15 bit converter, while for larger amplitude signals the SNR will not exceed that of a 10 bit converter.

Fig. 2.3
figure 3

Comparison of 10 and 15 bit linear ADCs to a floating point converter of 10 bit mantissa plus 5 bit dynamic range extension

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Floating point converters can also be derived from the linear successive-approximation ADC [3]. The modification can allow a reduction in the time needed to complete the quantization if a modified successive-approximation algorithm is used.

The performance of any converter can be improved if error sources are identified and reduced. An overview of common error sources in floating point converters and techniques to reduce the effects of the error sources are presented in [4]. Together with design techniques for the reduction of errors, calibration is another way of improving the performance of any converter. A background gain and offset calibration scheme is presented in [5].

Table 2.1 summarizes the characteristics of the most relevant pipeline and floating converters found in the literature.

Table 2.1 Pipeline and floating-point converters
Full size table

This ADC architecture does not implement a logarithmic transfer characteristic however it has some similarity to logarithmic converters where smaller quantization steps are user for input voltages with smaller amplitudes. The quantization step of floating-point converters changes abruptly with changes in the VGA gain setting, while for logarithmic converters the quantization step commonly has a progressive change throughout the input range.

2.2 Logarithmic Converters

Logarithmic converters can be derived from several linear architectures. Most examples found in the literature are derived from the linear pipeline or two-step architectures. This section complements and updates the work presented in [12].

In a logarithmic converter, the relationship between the input voltage and the output digital code can be expressed as:

$$Vin = K\left( {\frac{1}{K} + 1} \right)^{{\frac{OC}{{2^{N} - 1}}}}$$
(2.4)

where K is a compression coefficient, OC is the digital output code and N is the converter resolution in bits.

By changing K it is possible to adjust the characteristic of the logarithmic transfer function as can be seen on Fig. 2.4. This relationship is only valid for positive values of the input voltage Vin, if the converter needs to quantize both positive and negative values, the sign of the input voltage will resolve one bit and the logarithmic converter will need to quantize the module of the input voltage. The x-axis was normalized by subtracting K from the Vin obtained from (2.4) and the y-axis was normalized by dividing the output code \(OC\) by \(2^{N} - 1\).

Fig. 2.4
figure 4

Normalized logarithmic conversion characteristic

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The output digital code as a function of Vin, K and N is given by:

$$OC = \left( {2^{N} - 1} \right)\frac{{\ln \left( {\frac{Vin}{K}} \right)}}{{\ln \left( {1 + \frac{1}{K}} \right)}}; Vin > 0$$
(2.5)

For a logarithmic converter, the maximum dynamic range achievable is given by [13]:

$$DR_{dB} = 20log_{10} \frac{1}{{K\left( {\left( {1 + \frac{1}{K}} \right)^{{\frac{1}{{2^{N} - 1}}}} - 1} \right)}}$$
(2.6)

Whereas the maximum signal-to-noise ratio is given by:

$$SNR_{dB} = 10log_{10} \frac{{3 \cdot 2^{2N} }}{{ln\left( {1 + \frac{1}{K}} \right)^{2} }}$$
(2.7)

2.2.1 Logarithmic Pipeline Converters

The logarithmic function is obtained by changing the mathematical operations that each stage performs. Each linear operation is converted to its logarithmic equivalent, as exemplified in Fig. 2.5 [14,15,16,17,18]. Subtractions are replaced by an attenuation, additions are replaced by an amplification and the multiplication by two is replaced by a squaring function.

Fig. 2.5
figure 5

Linear to Logarithmic domain transformations

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Figure 2.6 shows one implementation of a logarithmic pipeline converter, which will only handle positive input voltages.

Fig. 2.6
figure 6

Logarithmic pipeline converter block diagram

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2.2.2 Two-Step Logarithmic Converters

Two-step logarithmic converters can employ a logarithmic amplification stage, which may be composed of one or more amplifiers, followed by a linear ADC as exemplified on Fig. 2.7.

Fig. 2.7
figure 7

Two-step logarithmic converter block diagram

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There are reports in the literature where this approach was taken by using COTS parts for the pre-amplifiers and ADC [19]. Another alternative is to use an approach closer to the one used for linear two-step converters, where the ADCs that determine the coarse and fine quantization work directly in the logarithmic domain [20]. Table 2.2 summarizes the characteristics of the most relevant logarithmic converters found in the literature.

Table 2.2 Logarithmic converters
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2.3 Piecewise Linear Converters

Piecewise linear converters are derived from the linear two step architectures, likewise, the conversion is also performed in two steps. In the first step a coarse quantization of the input is performed and the most significant bits are obtained, in the second step a fine quantization is performed and the least significant bits are obtained. The differences between the architectures are the quantizer reference voltages used for the first and second quantization steps.

In the conventional two-step architecture, the quantizer reference voltages of the coarse and fine quantization steps are equally spaced through the quantization range, this leads to a linear transfer characteristic. In the piecewise linear converter the quantizer reference voltages of the coarse step are not equally spaced through the quantization range. This results in an architecture that can approximate a continuous nonlinear transfer function with linear segments, hence the name piecewise linear. Some authors classify floating-point converters as piecewise linear converters, such as in [24].

One potential application where it is advantageous to use a piecewise linear converter is with nonlinear sensors. Application examples are presented in [25,26,27]. By using an appropriate ADC transfer characteristic it is possible to obtain a linearization of the sensor’s output, thus eliminating the need of post-acquisition nonlinearity correction. This allows the possibility of using cheaper, easier to manufacture or more power efficient sensors, since nonlinearities can be easily corrected and the nonlinearity correction is performed at acquisition speed.

Figure 2.8 shows the block diagram of one possible implementation of a piecewise linear converter. In the first quantization step, the sampled input voltage is compared with the reference voltage levels set in the first ADC, thus resolving N1 bits, and finding in which linear segment the second ADC will need to operate. The analog switch matrix then selects the reference voltages immediately above and below the sampled input voltage according to the result of the first quantization step. These voltages are buffered and used by the second ADC as upper and lower reference voltages to perform the second quantization step. The results of the two quantization steps are then joined and latched to form the complete output code. With this architecture it is possible to obtain any transfer characteristic as long as it is monotonic as exemplified on Fig. 2.9. On the left graph, the solid line represents the transfer characteristic of the process being quantized, such as the output of a sensor. The dashed line represents the inverse of the transfer characteristic of the process being quantized. The graph on the right represents the transfer characteristic of a piecewise linear ADC which approximates the inverse of the transfer characteristic of the process being quantized.

Fig. 2.8
figure 8

Piecewise linear converter block diagram

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Fig. 2.9
figure 9

Piecewise linear approximation to an arbitrary function

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Piecewise linear converters can be used to approximate logarithmic transfer functions. In this approach to obtaining a logarithmic transfer function, the breakpoints between the linear segments are selected in such a way that, the error between the desired logarithmic transfer function and the approximation is minimized. Figure 2.10 exemplifies how a piecewise linear converter can approximate a logarithmic transfer function.

Fig. 2.10
figure 10

Piecewise linear approximation to a logarithmic function

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As shown in Fig. 2.10, the input range of the piecewise linear converter is divided in subranges Ri, where each subrange can have a different size. The number of subranges is dependent on the number of bits, N1, resolved by the first ADC. For each subrange there will be a fixed number of output codes, the number of output codes is dependent on the number of bits, N2, resolved by the second ADC.

Table 2.3 summarizes the characteristics of the most relevant piecewise linear converters found in the literature.

Table 2.3 Piecewise linear converters
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2.4 Oversampled Converters

Unlike the Nyquist rate converters presented in previous sections, the oversampled converters operate at frequencies several times higher than the Nyquist frequency. The ratio between the sampling frequency and the Nyquist frequency is usually called Oversampling Ratio (OSR). In the oversampled converters there is a trade-off between sampling speed and resolution, for each clock cycle a reduced number of bits is resolved, which are then averaged, or decimated, to yield a lower frequency and higher resolution digital code.

2.4.1 Delta Converters

Delta converters are one of the simplest oversampled converters. The number of required parts is not very high, as shown on Fig. 2.11, thus, making this architecture a good candidate for low power applications.

Fig. 2.11
figure 11

Delta converter block diagram

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Converters can be characterized by their adaptability capabilities, that is, if the converter can adapt its sampling rate or quantization step size depending on the input signal. A converter which has the ability to adapt the step size is said to perform Adaptive Delta Modulation (ADM). If only the sample rate is adaptable, the converter is said to perform Nonuniform Sampling Delta Modulation (NS-DM). If both step size and sampling rate are adaptable the converter is said to perform Adaptive Nonuniform Sampling Delta Modulation (ANS-DM). By using NS-DM or ANS-DM the achievable SNR can be increased, a study of the companding and SNR gains for each of the modulation schemes is presented in [28].

Converters which perform ADM or ANS-DM can be classified according to the step size adaptation scheme, which can be continuously or discretely variable. Continuously variable slope delta modulation (CVSD) is generally performed by using an analog circuit. Discretely variable slope delta modulation (DVSD), as the name implies, is performed using digital circuitry.

Some techniques used with linear converters can also be used with nonlinear delta modulators, one of those techniques is time interleaving, as shown in [29]. Applications of nonlinear delta modulators include audio and image processing or coding [30,31,32] and sensor applications [29].

2.4.2 Sigma-Delta Converters

There are two classes of sigma-delta converters, the continuous time (CT) converters, where the loop filter is implemented by continuous integrators and the discrete time (DT) converters where the loop filter is implemented with switched capacitor circuits. Because DT converters are implemented with switched capacitor circuits, this makes them better suited for integration since their characteristics are defined by ratios of components, instead of having their characteristics defined by the absolute value of their components as is the case with CT converters.

Figure 2.12 shows the block diagram of the simplest discrete time sigma-delta converter, where the major building blocks can be identified. The sigma-delta converters modulate the digital output so as to reduce the accumulated error between the input signal and the output. One desirable characteristic of these converters is the distribution of the quantization noise, which is pushed outside the band of interest thus helping to improve the signal-to-noise ratio. One of the possible ways to obtain a nonlinear transfer characteristic with this type of converters is, to use a nonlinear ADC to sample the output of the integrator and a DAC that implements the inverse of the function used in the ADC [33].The CT converter for audio applications presented in [34] used this approach.

Fig. 2.12
figure 12

Sigma-Delta converter block diagram

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Another alternative is to place the nonlinear element before the integrator, and use a DAC that implements the inverse of the function used in the nonlinear element [35]. Table 2.4 summarizes the characteristics of the most relevant nonlinear sigma-delta converters found in the literature.

Table 2.4 Nonlinear sigma-delta converters
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2.5 Nonlinear Conversion Using Pulse Width Modulation

These architectures are interesting in the sense that there is an attempt to move most of the processing into digital blocks, one to a larger degree where an implementation uses an off-the-shelf microcontroller as will be shown in the following sub-sections.

2.5.1 Modified Integrating ADC

Nonlinear analog-to-digital conversion using PWM can be based on a modified integrating ADC scheme. As such the output code is obtained by counting how many clock periods elapse until the output voltage of an integrator equals the converter’s input signal [37]. In the example, presented in Fig. 2.13, there are three integrators from which to choose the voltage to compare with the input signal thus allowing the selection of different converter transfer characteristics.

Fig. 2.13
figure 13

Nonlinear PWM converter block diagram

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At the start of each conversion cycle all integrators and the counter are reset and the reference voltage is integrated. The value of the counter is incremented at each rising edge of the clock until the output of the selected integrator rises above the input voltage. At the end of the conversion cycle the value of the counter is latched to the output register and the process restarts. Figure 2.14 shows the evolution of the output voltage of the integrators, the input voltage of the converter and the clock signal. Figure 2.14 shows graphically the difference between the selectable transfer functions.

Fig. 2.14
figure 14

Evolution of the integration voltage for the linear, quadratic and cubic transfer characteristics

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The number of clock pulses counted is determined by the amount of time the output of the selected integrator is below the input voltage. If the reference voltage is integrated once, the time instant when the integrator’s output equals the input voltage is given by:

$$t_{linear} = \frac{Vin}{{IC_{1} Vref}}$$
(2.8)

where Vin is the input voltage, Vref is the reference voltage and IC1 is the time constant of the first integrator.

If the reference voltage is integrated twice, the time instant when the integrator’s output equals the input voltage is given by:

$$t_{quadratic} = \sqrt {\frac{2 Vin}{{IC_{1} IC_{2} Vref}}}$$
(2.9)

where IC2 is the time constant of the second integrator.

If the reference voltage is integrated three times, the time instant when the integrator’s output equals the input voltage is given by:

$$t_{cubic} = \sqrt[3]{{\frac{6 Vin}{{IC_{1} IC_{2} IC_{3} Vref}}}}$$
(2.10)

where IC3 is the time constant of the third integrators. The output code can be determined by:

$$Output\, Code = \frac{{t_{{\left\{ {linear,quadratic,cubic} \right\}}} }}{{T_{Clock} }}$$
(2.11)

where TClock is the clock period.

2.5.2 PWM Average Approximation

This conversion method is similar to a successive approximation scheme. Figure 2.15 shows a block diagram of a possible implementation where it can be seen that most of the processing is done digitally. It is therefore possible to implement this conversion scheme with contemporary microcontrollers that include comparators and PWM generators as peripherals. This type of architecture is very suitable for very low power dissipation, and the ADC characteristics can be easily adjusted to match what is required to convert the signal source, such as trading off resolution for speed. The transfer characteristic can also be easily adjusted given that the microcontroller can implement lookup tables or further signal processing.

Fig. 2.15
figure 15

AD converter using PWM signals and a COTS micro controller block diagram

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The conversion period is initiated by closing the switch S, which will allow the capacitor C to charge to the input voltage Vin through R1. After the capacitor C is charged, the switch S is opened and a PWM signal is injected through R2. The injected PWM signal has to be such that it will keep the capacitor voltage close to the input voltage Vin. The PWM signal is determined by comparing the voltage on capacitor C with the input voltage. If the capacitor voltage is below the input voltage, a logic high voltage (VH) is forced through R2 to make the voltage in the capacitor C rise. If the capacitor voltage is above the input voltage, a logic low voltage (VL) is forced through R2 to make the voltage in the capacitor C fall [38,39,40]. The VH and VL voltages determine the input range of the ADC, for input voltages above VH or below VL the converter will saturate.

The resolution of the converter can be adjusted in software by changing the total count of low and high pulses that are used to determine the result of the conversion.

2.6 Nonlinear Conversion Using a Lookup Table

This conversion scheme is the most generic and configurable of all the topologies presented. A lookup table is used to convert a linear value, obtained from a linear ADC, and converted it into an arbitrary value. The lookup table can be programmed to any desired transfer function thus allowing a very fine control of the transfer characteristic. If reprogramming is possible then it might be possible to fine tune the converter on-the-fly or completely change the transfer characteristic.

Figure 2.16 shows the block diagram of the most generic approach to this conversion scheme. However some improvements can be made in order to reduce the size of the lookup table and the resolution of the ADC that are needed.

Fig. 2.16
figure 16

Simple lookup table linear to logarithmic conversion

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Figure 2.17 shows the block diagram of the improved version of the converter. In the improved version, the resolution of the ADC equals the resolution needed by the application, as opposed to the simpler approach, where a high resolution code is fed to the lookup table to obtain a lower resolution output.

Fig. 2.17
figure 17

Optimized lookup table linear to logarithmic conversion

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The size of the lookup table is also reduced, the number of ROM addresses needed are 2N and 2M for the simple and improved versions respectively, since M < N there is a reduction in the number of addresses needed [22].

Implementation examples of converters using lookup tables can be found in [41, 42].

2.7 Other Architectures

There are converters that exhibit a logarithmic or non-uniform conversion characteristic without using the architectures described previously. One such example can be seen in [43], where a floating-point conversion characteristic is achieved without using a VGA at the input, as is common for traditional floating-point architectures. Other converters achieve a piecewise linear approximation to a logarithmic conversion characteristic by implementing a two-step conversion process employing a successive approximation scheme [44], where first coarse quantization step uses a logarithmic scale and the second fine quantization step used as linear scale. There are also examples of logarithmic conversion architectures doing the signal processing partly in the current domain and partly in the time domain [45, 46]. In these examples the sampled current is first compared with logarithmically weighted reference currents to perform a coarse quantization step, in a second step residue in the form of time is quantized by a logarithmic TDC. There is also a variation of this architecture where the first coarse logarithmic quantization step is performed in the current domain. In a second logarithmic fine quantization step a residue voltage is obtained by integrating a reference current for a fixed time and then comparing that voltage to a pseudo-exponential ramp [47].

2.8 Performance Metrics and Converter Testing

To compare the performance of converters with different characteristics, such as bandwidth and resolution a Figure of Merit (FOM) is usually used. Several FOM expressions can be found in the literature, however (2.12) and (2.13) are the most used to compare converters performance [48, 49], FOM1 and FOM2 are given in J/step. Expression (2.14) was used in [14] as an additional FOM metric when comparing nonlinear converters, FOM3 is given in dB.

$$FOM_{1} = \frac{P}{{Fs\,2^{ENOB} }}$$
(2.12)
$$FOM_{2} = \frac{P}{{Fs\,2^{2 ENOB} }}$$
(2.13)
$$FOM_{3} = 20log_{10} DR + 10log_{10} BW - 10log_{10} P$$
(2.14)

The variables P, Fs, ENOB, DR and BW represent the power dissipated by the circuit, sampling frequency, effective number of bits, dynamic range and input bandwidth of the converter, where the ENOB is given by:

$$ENOB = \frac{SNDR - 1.76}{6.02}$$
(2.15)

These are the metrics used to compare linear converters, however comparing nonlinear converters is not as straightforward. Different converters may have similar dynamic range but different SNR performance, or vice versa. Since these performance metrics are not as coupled together as in linear converters, using the same FOM determination method may not yield a useful result for comparison. Another difficulty in determining performance metrics is the lack of any generally accepted test method for nonlinear converters as there is for linear converters [50]. To compare FOM1 and FOM2 with FOM3 it was assumed that:

$$\begin{array}{*{20}c} {DR = 6.02 ENOB + 1.76} \\ {BW = \frac{Fs}{2}} \\ \end{array}$$
(2.16)

Figure 2.18 shows the change in the figures of merit as a function of power and sampling frequency when keeping the effective number of bit fixed with a value of 10 bit. The values of FOM1 and FOM2 decrease when the power decreases and the sampling frequency increases. The value of FOM3 decreases when the power increases and the sampling frequency decreases. Higher FOM1 or FOM2 values represent a worse figure of merit as a converter requires more power to perform the conversions at lower speeds while keeping the resolution constant, while for FOM3 lower values mean a worse figure of merit.

Fig. 2.18
figure 18

FOM versus power and sampling frequency

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Figure 2.19 shows the change in the figures of merit as a function of power and effective number of bits while keeping the sampling frequency fixed with a value of 100 MHz. The values of FOM1 and FOM2 decrease when the power decreases and the effective number of bits increases. The value of FOM3 decreases when the power increases and the effective number of bits decreases.

Fig. 2.19
figure 19

FOM versus power and effective number of bits

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Figure 2.20 shows the change in the figures of merit as a function of sampling frequency and effective number of bits while keeping the power fixed with a value of 1 mW. The values of FOM1 and FOM2 decrease when the effective number of bits increases and the sampling frequency increases. The value of FOM3 decreases when the sampling frequency decreases and the effective number of bits decreases. In this case the effect on the figure of merit of the change of the sampling frequency is stronger than the effect of the change in the effective number of bits.

Fig. 2.20
figure 20

FOM versus sampling frequency and effective number of bits

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Figure 2.21 shows a comparison of the architectures described previously. Since there isn’t a generally accepted metric to compare nonlinear converters, the number of samples per second and the resolution is bits were used.

Fig. 2.21
figure 21

Converter resolution versus sampling rate

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Converter testing is performed to access how close the converter is to the ideal transfer function. Typical metrics are the Integral Non-Linearity (INL), which measures the deviation of each code’s transition from the ideal transfer characteristic, the Differential Non-Linearity (DNL), which measures the deviation of the width of each quantization interval from the ideal value, and measures derived from the Fourier analysis of the quantization result, such as the Signal-to-Noise ratio (SNR), Signal-to-Noise Dynamic Range (SNDR) and Spurious Free Dynamic Range (SFDR).

For a linear converter, the INL is defined as:

$$INL\left( i \right) = \frac{{V_{Ti} - V_{T1} }}{{V_{LSB} }} - \left( {i - 1} \right); i = 1, \cdots ,2^{N} - 1$$
(2.17)

Likewise the DNL is defined as:

$$DNL\left( i \right) = \frac{{V_{{T\left( {i + 1} \right)}} - V_{Ti} }}{{V_{LSB} }} - 1; {\text{i}} = 1, \cdots ,2^{\text{N}} - 2.$$
(2.18)

With VLSB defined as:

$$V_{LSB} = \frac{{V_{{T\left( {2^{N} - 1} \right)}} - V_{T1} }}{{2^{N} - 1}}.$$
(2.19)

Where VT1 is the transition voltage of the first code, VTi is the transition voltage of code i and N is the number of bits.

These tests are performed according to a defined standard [50], however for nonlinear converters some of these tests may not yield meaningful results, such as some of the performance metrics obtained from the Fourier analysis. This is due to the nonlinear transfer characteristic of the converters and the inherent distortion introduced at the output. If the determination of the INL and DNL is done using the same definitions that are used for the linear converters the results will not be meaningful as explained in [51] using a logarithmic converter as example.

Determining the INL and DNL is usually based on a probabilistic test where, the number of occurrences of each code are counted, and then compared with the expected number of occurrences for an ideal converter [52]. The test signal usually used for testing is sinusoidal. Although other types of signals would make the analysis of the results simpler, it might not be possible to generate those signals with the precision required to properly test the converter. Any deviation from the ideal source, and the deviation will appear in the test result as errors. On the other hand, a sinusoidal signal with enough precision can be generated by successive filtering.

If a sinusoidal input signal is used to determine the INL and DNL of a nonlinear converter, the test may need much more samples than for the linear case. An example is shown in Fig. 2.22 where the occurrence of each code is plotted for a logarithmic and a linear converter. When using a sinusoidal test input signal, it can be clearly seen that for the logarithmic converter the mid-scale codes, corresponding to an input signal close to zero, have a very small number of occurrences.

Fig. 2.22
figure 22

Histogram of digital code distribution for a linear and a logarithmic converters

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To obtain the same bit precision and confidence interval as for the linear case a much larger sample set will be needed. Therefore alternative test methods must be used, such as the one presented in [53] for testing piecewise linear converters. For logarithmic converters it is advantageous to use alternative stimulus signals as shown in [51]. A test method using triangular small waves is presented in [54] where linearity requirements of the stimulus generator are relaxed.

If using the triangular small waves test with logarithmic converters, the DNL can be computed directly from the ratio of the bin width to the ideal bin width [13, 52]. In this case the DNL is given by:

$$DNL\left( i \right) = \frac{{\frac{H\left( i \right)}{{N_{t} }}}}{{a b^{{\frac{i}{{2^{N} - 1}}}} \left( {b^{{\frac{1}{{2^{N} - 1}}}} - 1} \right)}} - 1$$
(2.20)

where H(i) is the number of counts in the ith bin, N is the number of bits and a and b are given by:

$$\begin{array}{*{20}l} {a = K} \hfill \\ {b = 1 + \frac{1}{K}} \hfill \\ \end{array}$$
(2.21)

where K is the compression coefficient.

This test method may be a good candidate for testing nonlinear converters since only small ranges of the full quantization interval are excited at any given time, therefore the test profile can be adjusted to minimize the test duration and the number of samples acquired during the test. Discontinuity zones, such as the breakpoints of piecewise-linear converters or the gain transition points in floating-point converters, can be directly tested without the need to sweep the entire quantization range.

2.9 Conclusions

Linear analog-to-digital signal conversion is the most common way to quantize a signal of interest, and for many applications that is the adequate choice. Linear signal conversion retains the finer details of the signal of interest regardless of the signal’s amplitude even if the finer details are not important when the signal’s amplitude is large, also as the name implies, a linear converter ideally will not introduce distortion in the conversion’s result.

Nonlinear conversion can allow a compromise between the converter’s resolution and the smallest signal variation that can be resolved for large signal amplitudes, this can introduce distortions in the conversion’s result and can be desirable as a way to compensate or linearize the input signal, for example as a way to linearize a sensor’s response. A specific case of nonlinear converters is the logarithmic converter where the conversion characteristic performs a fine quantization of signals with small amplitude and a coarser quantization of signals with large amplitude. Application fields where the logarithmic characteristic is useful or desirable range from biomedical applications to telecommunications and state of the art data storage, and in general applications where a large dynamic range is required but the conversion resolution of a linear converter with a similar dynamic range is not needed.

In this Chapter the different nonlinear analog-to-digital converter architectures that have been found in the literature to implement diverse nonlinear analog-to-digital transfer characteristics and in particular a logarithmic characteristic have been presented. The operating mode of the presented architectures has been described and brief summary tables with the disclosed performance data have been compiled for each of the presented architectures.

A short overview of the performance metrics used to compare converters has been given. The different figure of merit metrics found in the literature have been presented, however these may not present a fair comparison when linear and nonlinear converters are compared.

The performance testing of nonlinear converters has also been discussed, as the methods used for testing linear converters are not adequate for testing nonlinear converters.