Abstract
The purpose of this paper is to propose a bilateral key confirmation scheme which provides a trustworthy key establishment between two communicating parties. There are various cryptographic schemes proposed based on unilateral key confirmation. But, such schemes do not confirm the equality of the common secret information computed independently by each communicating party, and do not consider whether the other end is the intended owner of the shared secret. However, exchanging of the secret information blindly without verifying that both of the ends have computed the same common secret information and without ensuring the identity of the other end with whom they are communicating, can create security risks since attackers can impersonate acting as a claimed sender or recipient. The proposed work provides bilateral key confirmation for pair-wise key-establishment based on FPGA by integrating a key agreement protocol and an authenticated encryption scheme. The implementation outcomes show the proposed scheme’s reasonable hardware complexity and enhanced performance compared to existing similar works.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Diffie, W., Hellman, M.: New directions in cryptography. IEEE Trans. Inf. Theory 22(6), 644–654 (1976)
Boneh, D., Shparlinski, I.E.: On the unpredictability of bits of the elliptic curve Diffie-Hellman scheme. In: Kilian, J. (ed.) CRYPTO 2001. LNCS, vol. 2139, pp. 201–212. Springer, Heidelberg (2001). https://doi.org/10.1007/3-540-44647-8_12
Rivest, R., Shamir, A., Adleman, L.: A method for obtaining digital signatures and public-key cryptosystems. ACM Trans. Commun 21, 120–126 (1978)
Gutub, A.A., Khan, F.A.: Hybrid crypto hardware utilizing symmetric-key & public-key cryptosystems. In: IEEE International Conference on Advanced Computer Science Applications and Technologies (ACSAT), pp. 116–121 (2013)
Nadjia, A., Mohamed, A.: AES IP for hybrid cryptosystem RSA-AES. In: IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD 2015), pp. 1–6 (2015)
Kapur, R.K., Khatri, S.K.: Secure data transfer in MANET using symmetric and asymmetric cryptography. In: IEEE International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), pp. 1–5 (2015)
Abdalla, M., Bellare, M., Rogaway, P.: The oracle Diffie-Hellman assumptions and an analysis of DHIES. In: Naccache, D. (ed.) CT-RSA 2001. LNCS, vol. 2020, pp. 143–158. Springer, Heidelberg (2001). https://doi.org/10.1007/3-540-45353-9_12
Martínez, V.G., Alvarez, F.H., Encinas, L.H., Ávila, C.S..: A comparison of the standardized versions of ECIES. In: IEEE Sixth International Conference on Information Assurance and Security (2010)
Martínez, V.G., Álvarez, F.H., Encinas, L. H.: Analysis of ECIES and other cryptosystems based on elliptic curves. CSIC Digital (2013)
Barker, E., Chen, L., Roginsky, A., Vassilev, A., Davis, R.: Recommendation for Pair-Wise Key-Establishment Schemes Using Discrete Logarithm Cryptography. NIST Special Publication 800-56A Revision 3, April 2018
Dworkin, M.: NIST Special Publication 800-38D: Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC (2007)
Federal Information Processing Standards (FIPS) Publication 180-4,: Secure Hash Standard (SHS), vol. 4 (2015)
Satoh, A., Sugawara, T., Aoki, T.: High-speed pipelined hardware architecture for Galois counter mode. In: Garay, J.A., Lenstra, A.K., Mambo, M., Peralta, R. (eds.) ISC 2007. LNCS, vol. 4779, pp. 118–129. Springer, Heidelberg (2007). https://doi.org/10.1007/978-3-540-75496-1_8
Wang, J., Shou, G., Hu, Y., Guo, Z.: High-speed architectures for GHASH based on efficient bit-parallel multipliers. In: IEEE International Conference on Wireless Communications, Networking and Information Security (WCNIS), pp. 582–586 (2010)
Mastrovito, E.D.: VLSI architectures for computations in Galois fields. Ph.D. thesis, Linköping University, Department of Electrical Engineering, Linköping, Sweden (1991)
Montgomery, P.: Modular multiplication without trial division. Math. Comput. 44, 519–521 (1985)
Zhou, G., Michalik, H., Hinsenkamp, L.: Improving throughput of AES-GCM with pipelined karatsuba multipliers on FPGAs. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds.) ARC 2009. LNCS, vol. 5453, pp. 193–203. Springer, Heidelberg (2009). https://doi.org/10.1007/978-3-642-00641-8_20
Abdellatif, K.M., Chotin-Avot, R., Mehrez, H.: Authenticated encryption on FPGAs from the static part to the reconfigurable part. Microprocess. Microsyst. 38(6), 526–538 (2014)
Abdellatif, K.M., Chotin-Avot, R., Mehrez, H.: AES-GCM and AEGIS: efficient and high speed hardware ımplementations. J. Signal Process. Syst. 88(1), 1–12 (2017)
Sandoval, M.M., Uribe, C.F.: A hardware architecture for elliptic curve cryptography and lossless data compression. In: IEEE International Conference on Electronics, Communications and Computers, pp. 113–118 (2005)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Tadesse Abebe, A., Negash Shiferaw, Y., Gebeye Abera, W., Kumar, P.G.V.S. (2019). Efficient FPGA Implementation of an Integrated Bilateral Key Confirmation Scheme for Pair-Wise Key-Establishment and Authenticated Encryption. In: Zimale, F., Enku Nigussie, T., Fanta, S. (eds) Advances of Science and Technology. ICAST 2018. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 274. Springer, Cham. https://doi.org/10.1007/978-3-030-15357-1_36
Download citation
DOI: https://doi.org/10.1007/978-3-030-15357-1_36
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-15356-4
Online ISBN: 978-3-030-15357-1
eBook Packages: Computer ScienceComputer Science (R0)