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Multi-level Memristive Memory for Neural Networks

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Deep Learning Classifiers with Memristive Networks

Part of the book series: Modeling and Optimization in Science and Technologies ((MOST,volume 14))

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Abstract

Analog memory is of great importance in neuromorphic engineering as it enables scalable neural network design and energy efficient implementation of computationally expensive operations. With the advent of memristors, the realization of the analog memory became possible due to the intrinsic properties of memristors such as nanoscale size, non-volatility, and energy efficiency. In hardware implementations of neural networks, memristors store the values of synaptic weights and operate similarly to the synapses that are reinforced with the application of external stimuli. Memristors that are ideally continuum memories, currently are at the early stage of the development, which causes several issues in neuromorphic circuit design. Device level and architecture level issues force memory engineers to approach memristive memory design in different ways. In this chapter device-level problems: restricted number of resistance states, stochastic switching and architecture level problem: sneak paths will be discussed, and their state of the art solutions will be presented.

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Authors and Affiliations

  1. Nazabayev University, Astana, Kazakhstan

    Aidana Irmanova, Serikbolsyn Myrzakhmet & Alex Pappachen James

Authors
  1. Aidana Irmanova
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  2. Serikbolsyn Myrzakhmet
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  3. Alex Pappachen James
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Corresponding author

Correspondence to Alex Pappachen James .

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Editors and Affiliations

  1. School of Engineering, Nazarbayev University, Astana, Kazakhstan

    Alex Pappachen James

Chapter Highlights

Chapter Highlights

  • An analog memory cell in crossbar circuits store synaptic weights of NN.

  • In the ideal case, an analog memory cell based on single memristor in crossbar circuits store infinite synaptic weight values.

  • In practice memristors store discrete resistive states. A memory cell consisting of a combination of parallel or series memristors can be used to increase stored resistive levels.

  • During the inference stage of neural networks, reading voltages are used to avoid resistive switching.

  • During the training stage of neural networks, programming voltages are used to force the resistive switching.

  • The sneak path takes place in memristive crossbar arrays complicating inference and training processes of the system. Possible sneak path solutions suitable for developing a multilevel memory include designing unfolded architecture, diode gating, and transistor gating.

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Irmanova, A., Myrzakhmet, S., James, A.P. (2020). Multi-level Memristive Memory for Neural Networks. In: James, A. (eds) Deep Learning Classifiers with Memristive Networks. Modeling and Optimization in Science and Technologies, vol 14. Springer, Cham. https://doi.org/10.1007/978-3-030-14524-8_8

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