Skip to main content
SpringerLink
Log in
Book cover

Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors pp 87–126Cite as

Ultra-Low Voltage Microcontrollers

  • Chapter
  • First Online:

Abstract

To leverage the design strategy presented in Chap. 3 to its full capability, this chapter implements a state-of-the-art microcontroller system. The main goal is to provide a proof-of-concept implementation on an industry-proven design to showcase the efficacy of the mentioned strategy, as well as achieve excellent energy and speed performance. The ARM Cortex-M0 core is chosen to this end. It is used in a variety of commercial systems going from IoT nodes (Sparkfun, NEST: Nest Thermostat Teardown. https://learn.sparkfun.com/tutorials/nest-thermostat-teardown- (2016); TechInsights, Fitbit: Fitbit Charge 2 Teardown. http://www.techinsights.com/about-techinsights/overview/blog/fitbit-charge-2-teardown/) to virtual reality (VR) glasses (IFixit, Oculus-VR: Oculus Rift CV1 Teardown - iFixit. https://www.ifixit.com/Teardown/Oculus+Rift+CV1+Teardown/60612, 2016). The core is ideally suited for energy-constrained applications, so it has been a recurrent topic in low voltage literature as well.

This chapter will demonstrate how the architecture of the microcontroller system came to be in Sect. 4.2. It includes the M0 core, a memory and the necessary peripherals for interfacing and debugging. The framework to program the system is fully compatible with the ARM tool chain. It allows arbitrary C-code to be programmed and run on the core. Section 4.3 dives deeper in the implementation details of the presented system. Two distinct silicon implementations of the same system have been realized. A number of considerations necessary for ultra-low voltage operation are discussed. The measurements presented in Sect. 4.4 demonstrate the state-of-the-art performance of the prototypes. They excel in speed performance and ultra-low energy consumption. The memory system power and the overall standby power leave room for improvement. Section 4.5 provides more details on the energy consumption and how it is improved between both prototypes. The state-of-the-art comparison in Sect. 4.6 further demonstrates the good performance of the prototypes. Finally, some concluding remarks regarding the system and its performance can be found in Sect. 4.7.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Abouzeid, F., Clerc, S., Bottoni, C., Coeffic, B., Daveau, J.M., Croain, D., Gasiot, G., Soussan, D., Roche, P.: 28 nm FD-SOI technology and design platform for sub-10 pJ/cycle and SER-immune 32bits processors. In: 41st IEEE European Conference on Solid-State Circuits (ESSCIRC), pp. 108–111. IEEE, Piscataway (2015)

    Google Scholar 

  2. ARM: AMBA 3 AHB-Lite Protocol Specification v1.0 Arm Developer. https://developer.arm.com/docs/ihi0033/a/amba-3-ahb-lite-protocol-specification-v10

  3. ARM: ARM Cortex-M series processors overview. https://www.arm.com/products/processors/cortex-m

  4. ARM: DesignStart for University arm. https://www.arm.com/resources/designstart/designstart-university

  5. Ashouei, M., Hulzink, J., Konijnenburg, M., Zhou, J., Duarte, F., Breeschoten, A., Huisken, J., Stuyt, J., de Groot, H., Barat, F., David, J., Van Ginderdeuren, J.: A voltage-scalable biomedical signal processor running ECG using 13 pJ/cycle at 1 MHz and 0.4 V. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 332–334. IEEE, Piscataway (2011)

    Google Scholar 

  6. Bol, D., De Vos, J., Hocquet, C., Botman, F., Durvaux, F., Boyd, S., Flandre, D., Legat, J.D.: SleepWalker: a 25-MHz 0.4-V Sub-mm2 7-uW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. IEEE J. Solid State Circuits 48(1), 20–32 (2013)

    Google Scholar 

  7. Bowman, K., Duvall, S., Meindl, J.: Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits 37(2), 183–190 (2002)

    Article  Google Scholar 

  8. Chen, W., Hancke, G., Mayes, K., Lien, Y., Chiu, J.H.: NFC mobile transactions and authentication based on GSM network. In: Second International Workshop on Near Field Communication, pp. 83–89. IEEE, Piscataway (2010)

    Google Scholar 

  9. Chen, J.S., Yeh, C., Wang, J.S.: Self-super-cutoff power gating with state retention on a 0.3 V 0.29 fJ/cycle/gate 32 b RISC core in 0.13 um CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 426–427. IEEE, Piscataway (2013)

    Google Scholar 

  10. Cobham Gaisler: Leon/GRLIB. https://www.gaisler.com/

  11. Craig, K., Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., Calhoun, B.H.: A 32 b 90 nm processor implementing panoptic dvs achieving energy efficient operation from sub-threshold to high performance. IEEE J. Solid-State Circuits 49(2), 545–552 (2014)

    Article  Google Scholar 

  12. Flynn, D., Wood, T., Dworsky, P., Melikyan, V., Babayan, E.: Teaching IC design with the ARM Cortex-M0 designstart processor and synopsys 90 nm educational design kit. In: 3rd Interdisciplinary Engineering Design Education Conference, pp. 36–38. IEEE, Piscataway (2013)

    Google Scholar 

  13. Hamacher, V., Kornagel, U., Lotter, T., Puder, H.: Binaural signal processing in hearing aids: technologies and algorithms. In: Advances in Digital Speech Transmission, pp. 401–429. Wiley, Chichester (2008)

    Google Scholar 

  14. IFixit, Oculus-VR: Oculus Rift CV1 Teardown - iFixit. https://www.ifixit.com/Teardown/Oculus+Rift+CV1+Teardown/60612 (2016)

  15. Jain, S., Khare, S., Yada, S., Ambili, V., Salihundam, P., Ramani, S., Muthukumar, S., Srinivasan, M., Kumar, A., Gb, S.K., Ramanarayanan, R., Erraguntla, V., Howard, J., Vangal, S., Dighe, S., Ruhl, G., Aseron, P., Wilson, H., Borkar, N., De, V., Borkar, S.: A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 66–68. IEEE, Piscataway (2012)

    Google Scholar 

  16. Jin, W., Kim, S., He, W., Mao, Z., Seok, M.: In situ error detection techniques in ultralow voltage pipelines: analysis and optimizations. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(3), 1032–1043 (2017)

    Article  Google Scholar 

  17. Jock, S.C., Bolus, J.F., Wooters, S.N., Jurik, A.D., Weaver, A.C., Blalock, T.N., Calhoun, B.H.: A 2.6-uW sub-threshold mixed-signal ECG SoC. In: IEEE Symposium on VLSI Circuits (VLSI) (2009)

    Google Scholar 

  18. Kim, S., Mingoo Seok: R-processor: 0.4 V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65 nm CMOS. In: Symposium on VLSI Circuits Digest of Technical Papers (VLSI), pp. 1–2. IEEE, Piscataway (2014)

    Google Scholar 

  19. Kim, H., Kim, S., Van Helleputte, N., Artes, A., Konijnenburg, M., Huisken, J., Van Hoof, C., Yazicioglu, R.F.: A configurable and low-power mixed signal SoC for portable ECG monitoring applications. IEEE Trans. Biomed. Circuits Syst. 8(2), 257–267 (2014)

    Article  Google Scholar 

  20. Kwong, J., Ramadass, Y.K., Verma, N., Chandrakasan, A.P.: A 65 nm Sub-V t microcontroller with integrated SRAM and switched capacitor DC-DC converter. IEEE J. Solid State Circuits 44(1), 115–126 (2009)

    Article  Google Scholar 

  21. Lallement, G., Abouzeid, F., Cochet, M., Daveau, J.M., Roche, P., Autran, J.L.: A 2.7 pJ/cycle 16 MHz SoC with 4.3 nW power-off ARM Cortex-M0+ core in 28 nm FD-SOI. In: 43rd IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 153–162. IEEE, Piscataway (2017)

    Google Scholar 

  22. Lallement, G., Abouzeid, F., Cochet, M., Daveau, J.M., Roche, P., Autran, J.L.: A 2.7 pJ/cycle 16 MHz, 0.7 μW deep sleep power ARM Cortex-M0+ core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits 53(7), 2088–2100 (2018)

    Google Scholar 

  23. Lim, W., Lee, I., Sylvester, D., Blaauw, D.: Batteryless Sub-nW cortex-M0+ processor with dynamic leakage-suppression logic. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 1–3. IEEE, Piscataway (2015)

    Google Scholar 

  24. Lin, L., Jain, S., Alioto, M.: A 595 pW 14 pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 44–46. IEEE, Piscataway (2018)

    Google Scholar 

  25. Luetkemeier, S., Jungeblut, T., Porrmann, M., Rueckert, U.: A 200 mV 32b subthreshold processor with adaptive supply voltage control. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 484–486. IEEE, Piscataway (2012)

    Google Scholar 

  26. Mäkipää, J., Turnquist, M.J., Laulainen, E., Koskinen, L.: Timing-error detection design considerations in subthreshold: an 8-bit microprocessor in 65 nm CMOS. J. Low Power Electr. Appl. 2(2), 180–196 (2012)

    Article  Google Scholar 

  27. Markovic, D., Wang, C., Alarcon, L., Liu, T.T, Rabaey, J.: Ultralow-power design in near-threshold region. Proc. IEEE 98(2), 237–252 (2010)

    Article  Google Scholar 

  28. Myers, J., Savanth, A., Howard, D., Gaddh, R., Prabhat, P., Flynn, D.: An 80 nW retention 11.7 pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65 nm CMOS for WSN applications. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 1–3. IEEE, Piscataway (2015)

    Google Scholar 

  29. Myers, J., Savanth, A., Gaddh, R., Howard, D., Prabhat, P., Flynn, D.: A subthreshold ARM Cortex-M0+ subsystem in 65 nm CMOS for WSN applications with 14 power domains, 10T SRAM, and integrated voltage regulator. IEEE J. Solid State Circuits 51(1), 31–44 (2016)

    Article  Google Scholar 

  30. Nachman, L., Huang, J., Shahabdeen, J., Adler, R., Kling, R.: IMOTE2: serious computation at the edge. In: International Conference on Wireless Communications and Mobile Computing, pp. 1118–1123. IEEE, Piscataway (2008)

    Google Scholar 

  31. Paul, S., Honkote, V., Kim, R.G., Majumder, T., Aseron, P.A., Grossnickle, V., Sankman, R., Mallik, D., Wang, T., Vangal, S., Tschanz, J.W., De, V.: A sub-cm3 energy-harvesting stacked wireless sensor node featuring a near-threshold voltage IA-32 microcontroller in 14-nm tri-gate CMOS for always-ON always-sensing applications. IEEE J. Solid State Circuits 52(4), 961–971 (2017)

    Article  Google Scholar 

  32. Pestana, J., Sanchez-Lopez, J.L., Saripalli, S., Campoy, P.: Computer vision based general object following for GPS-denied multirotor unmanned vehicles. In: American Control Conference, pp. 1886–1891. IEEE, Piscataway (2014)

    Google Scholar 

  33. Reyserhove, H., Dehaene, W.: A 16.07pJ/cycle 31 MHz fully differential transmission gate logic ARM cortex M0 core in 40 nm CMOS. In: 42nd IEEE European Conference on Solid-State Circuits (ESSCIRC), pp. 257–260. IEEE, Piscataway (2016)

    Google Scholar 

  34. Reyserhove, H., Dehaene, W.: A Differential transmission gate design flow for minimum energy sub-10-pJ/Cycle ARM Cortex-M0 MCUs. IEEE J. Solid State Circuits 52(7), 1904–1914 (2017)

    Article  Google Scholar 

  35. Rooseleer, B., Cosemans, S., Dehaene, W.: A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link. IEEE J. Solid State Circuits 47(7), 1784–1796 (2012)

    Google Scholar 

  36. Seok, M., Blaauw, D., Sylvester, D.: Clock network design for ultra-low power applications. In: Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), p. 271. IEEE, Piscataway (2010)

    Google Scholar 

  37. Sharma, V., Cosemans, S., Ashouie, M., Huisken, J., Catthoor, F., Dehaene, W.: Ultra low-energy SRAM design for smart ubiquitous sensors. IEEE Micro 32(5), 10–24 (2012)

    Article  Google Scholar 

  38. Sparkfun, NEST: Nest Thermostat Teardown. https://learn.sparkfun.com/tutorials/nest-thermostat-teardown- (2016)

  39. TechInsights, Fitbit: Fitbit Charge 2 Teardown. http://www.techinsights.com/about-techinsights/overview/blog/fitbit-charge-2-teardown/

  40. Wang, J.S., Chen, J.S., Wang, Y.M., Yeh, C.: A 230 mV-to-500 mV 375 KHz-to-16 MHz 32b RISC Core in 0.18 μm CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 294–604. IEEE, Piscataway (2007)

    Google Scholar 

  41. Warneke, B., Pister, K.: An ultra-low energy microcontroller for Smart Dust wireless sensor networks. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 316–317. IEEE, Piscataway (2004)

    Google Scholar 

  42. Weicker, R.P.: Dhrystone benchmark (version 2.1) http://groups.google.com/group/comp.arch/browse_thread/thread/b285e89dfc1881d3/068 (1988)

  43. Yiu, J.: The definitive guide to the ARM Cortex-M0 (2011)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ESAT—MICAS, KU Leuven, Seattle, USA

    Hans Reyserhove

  2. KU Leuven, Heverlee, Belgium

    Wim Dehaene

Authors
  1. Hans Reyserhove
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Wim Dehaene
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Reyserhove, H., Dehaene, W. (2019). Ultra-Low Voltage Microcontrollers. In: Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors. Springer, Cham. https://doi.org/10.1007/978-3-030-12485-4_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-12485-4_4

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-12484-7

  • Online ISBN: 978-3-030-12485-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation