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A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis

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Book cover Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

This chapter introduces an analog fractional-N subsampling PLL that relies on a digital-to-time (DTC) converter in the phase-error comparison path for fractional residue compensation. Since the DTC is put at the input of the system, its resolution, linearity, and phase noise performance introduce the bottleneck for the overall spectral purity. A high-efficiency, low-noise 10-bit DTC with 0.5 ps resolution is designed. Analog sensitivities of the circuit (such as DTC gain variation) are compensated in the digital domain. The prototype achieves a robust fractional lock across the range from 9.2 GHz to 12.7 GHz with less than 280-fs rms integrated jitter (in presence of the worst fractional spur). The total power consumption of the PLL is 13 mW.

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Notes

  1. 1.

    Note that the skipping operation is possible thanks to the sinusoidal detection gain of the subsampling PLL, which repeats every T VCO.

  2. 2.

    A first-order Δ Σ generates modulation of only 1. This means that the DTC operates with delays of up to a single VCO period. A popular MASH 1-1-1 modulator has an output range of 7, which is reduced after some filtering in the phase accumulator.

  3. 3.

    PLL multiplication factor N is 250 in this example, and phase noise is multiplied by N 2 in transfer to the output (in PLL band).

  4. 4.

    For instance, the digital controller features a full lookup table of the DTC, which is built with 10k flip-flops. The LUT was programmed with a perfectly linear mapping. It was, therefore, not necessary.

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Authors and Affiliations

  1. IMEC, Leuven, Belgium

    Nereo Markulic, Kuba Raczkowski, Jan Craninckx & Piet Wambacq

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  1. Nereo Markulic
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Markulic, N., Raczkowski, K., Craninckx, J., Wambacq, P. (2019). A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis. In: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-10958-5_2

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  • DOI: https://doi.org/10.1007/978-3-030-10958-5_2

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  • Online ISBN: 978-3-030-10958-5

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