Abstract
In this chapter, we will look at modeling sequential storage devices. We begin by looking at modeling scalar storage devices such as D-latches and D-flip-flops and then move into multiple-bit storage models known as registers.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this chapter
Cite this chapter
LaMeres, B.J. (2019). Modeling Sequential Storage and Registers. In: Quick Start Guide to Verilog. Springer, Cham. https://doi.org/10.1007/978-3-030-10552-5_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-10552-5_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-10551-8
Online ISBN: 978-3-030-10552-5
eBook Packages: EngineeringEngineering (R0)