Test Benches

Abstract

One of the essential components of the modern digital design flow is verifying functionality through simulation. This functional verification is accomplished using a test bench. A test bench is a Verilog model that instantiates the system to be tested as a subsystem, generates the input patterns to drive into the subsystem, and observes the outputs. Test benches are only used for simulation, so they can use abstract modeling techniques that are unsynthesizable to generate the stimulus patterns. Verilog conditional programming constructions and system tasks can also be used to report on the status of a test and also automatically check that the outputs are correct. This chapter provides the details of Verilog’s built-in capabilities that allow test benches to be created and some examples of automated stimulus generation.